Forum Discussion
aucamera1
New Contributor
New ContributorHPS f2sdram read/write errors
I'm using the Agilex 5 devlopment board and trying to write to the HPS SDRAM with custom logic. I'm already able to write to the other SDRAM (DDR4) on the board with my custom logic going through th...
Nirav_AlteraNew Contributor
New ContributorHello aucamera1,
One clarification: Are you running an FPGA-only design, or is the HPS also being booted (SPL/ATF/U-Boot) before you access F2SDRAM?
aucamera1New Contributor
New ContributorNirav_Altera , yes, the HPS is booted and running
- Yoda_Altera
Hello aucamera1,
I am Jeff, the Agilex 5 HPS / HPS-EMIF expert at Altera.
- How much DDR4 do you have attached to the HPS? 8GB?
- See the memory map at:
https://docs.altera.com/r/docs/814346/25.3.1/hard-processor-system-technical-reference-manual-agilextm-5-socs/total-address-map-graphical
- The addresses from the FPGA perspective to SDRAM (F2SDRAM) (blue regions) are:
- 0x00_8000_0000 - 0x01_0000_0000 (first 2 GB of DDR)
- 0x08_8000_0000 - 0x10_0000_0000 (next 30 GB of DDR)
- 0x88_0000_0000 - 0xFF_FFFF_FFFF (next 480 GB of DDR)
- So, please try read/write to somewhere in the range of DDR attached, such as 0x00_8000_0000 (which is really @ 0x0 of the attached DDR) or 0x08_8000_0000 (which is really @ 2GB of the attached DDR).
- BUT.... be careful because you could be "modifying" anything that is out in the HPS DDR, such as Linux OS, etc.
- Lastly, can you explain what you mean by:
- I'm already able to write to the other SDRAM (DDR4) on the board with my custom logic going through the AXI4 bus
If the above does not work, then we need to focus on making sure the F2SDRAM bridge is properly open and there are no OS blocking issues and/or firewall issues.
Regards,
Jeff
