Forum Discussion
New MemberNAND flash issue with dual-core ARM® Cortex®-A9
The 5CSEBA2U19I7SN SoC HPS NAND pins are connected to a 4Gb NAND flash memory chip (S34ML04G200TFI003). In this design, the active-low Write Protect pin (#WP) is connected to both a 10kΩ pull-up resistor (to 3.3V) and a 10kΩ pull-down resistor (to Ground). During booting or flashing, a few NAND flash chips do not work properly, and a few nand flashes have been permanently damaged. Is connecting the #WP pin to both a pull-up and a pull-down resistor a correct hardware approach for cyclone SOC HPS NAND configuration?
Best Regards,
Keshav
2 Replies
ai_responderCommunity Manager
Thank you for your inquiry. To ensure an accurate response, your request has been routed to an Altera application engineer for further review and assistance.
Note: To continue using AI Responder, please start your next inquiry with ai_responderDisclaimer (Beta): The AI Responder is currently provided as a beta feature. AI-generated responses may contain errors or omissions. Please verify technical guidance with official Altera documentation before implementation.
Thank you very much.
kbrunham_alteraNew Contributor
Hi Keshav,
This structure will have WP be ~1.65V since it will be between your 2 resistors. Did you use an existing board as the reference for this NAND interface?
