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Occasional ContributorSubject: [Arria 10 SoC] QSPI Flash Macronix Compatibility (MX66U2G45GXRI00)
Hi Altera Community Support Team,
We are currently using the Micron MT25QU02G as the primary QSPI boot device for our Arria 10 SoC (HPS) board. However, due to a severe unit price increase (nearly 20x), we are urgently looking for a cost-effective alternative QSPI Flash memory.
We are currently considering Macronix devices as potential replacements. The Macronix distributor has specifically recommended using the MX66U2G45GXRI00 instead of the MX66U2G45GXRI54.
Could you please provide a technical review on whether the MX66U2G45GXRI00 can be used as a direct replacement? Specifically, I would like to ask the following questions:
Arria 10 SoC Compatibility: Does the Arria 10 SoC HPS BootROM support booting from the Macronix MX66U2G45GXRI00? Since the BootROM operates using standard JEDEC SFDP and basic SPI opcodes, can we expect it to load the preloader/U-Boot SPL without issue?
Programming Tooling: Will quartus_hps or the HPS Flash Programmer support flashing this Macronix part directly, or would we need to handle programming via U-Boot / JTAG scripts?
Any advice, official guidance, or experience regarding Macronix QSPI Flash migration on the Arria 10 SoC would be greatly appreciated.
3 Replies
spacechips-llcNew Contributor
1. Why the Distributor Recommended `MX66U2G45GXRI00` over `...54`
The distributor's recommendation is critical and correct:
* **`MX66U2G45GXRI54` ("54" Version):** Factory-configured with **Permanent 4 I/O (Permanent Quad Mode), Permanent 4-Byte Address Mode, and fixed dummy cycles (10 cycles)**.
* **`MX66U2G45GXRI00` ("00" Version):** The standard, backward-compatible version that powers up in **Standard SPI mode (1-bit / Single I/O)** and defaults to **3-Byte Address Mode**.
**Why this matters for Arria 10 HPS BootROM:**
The Arria 10 HPS BootROM **cannot boot from the "54" version**.
On cold boot / power-on reset, the Arria 10 HPS BootROM initializes the Cadence QSPI controller using hardcoded register defaults:
* Single I/O (1-bit data width, 1-bit address width)
* Standard 3-byte address mode (`numaddrbytes = 2` in the `devsz` register)
* Standard read opcode `0x03` (Normal Read) or `0x0B` (Fast Read)
Because the **"54"** version boots up with 1-bit SPI disabled (locked in Quad mode) and expects 4-byte addressing, the BootROM will fail immediately. The **`MX66U2G45GXRI00`** is mandatory because it powers on in standard 1-bit SPI mode with 3-byte addressing.
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### 2. Arria 10 SoC BootROM & Architecture Compatibility
#### A. Misconception on SFDP in BootROM
Contrary to common belief, the **Arria 10 HPS BootROM does not parse JEDEC SFDP tables**.
The BootROM executes hardcoded, fixed-configuration read cycles. As long as the flash:
1. Powers up in standard 1-bit SPI (`0x03` or `0x0B` compatible).
2. Operates within the 1.8V power rail (`BSEL = 0x6`).
3. Responds to 3-byte addressing for the initial 16 MB memory window,
the BootROM will locate the boot header and load the U-Boot SPL / preloader into OCRAM.
#### B. The 2Gb (256MB) > 16MB Addressing Trap
Because this is a 2Gb device:
* The BootROM can only address the lower **16 MB (128 Mb)** of flash using standard 3-byte addresses.
* **Rule:** Your U-Boot SPL image must be located within the first 16 MB.
* Once U-Boot SPL takes control, the Cadence QSPI driver enters 4-byte address mode (`0x13` / `0x0C` opcodes or entering 4-byte mode via `0xB7`) to load U-Boot proper and the Linux kernel/FPGA bitstream from upper sectors.
* **Critical Warm Reset Requirement:** If the system undergoes a warm reset while the flash is left in 4-byte mode, the BootROM will crash upon reboot. Ensure your board ties the **HPS cold/warm reset to the hardware `RESET#` pin of the MX66U2G45G** (or enable soft-reset `0x66`/`0x99` handling) so the flash resets back to 3-byte default mode upon CPU reboot.
- HPark14
Thank you for your reply.
I will try the 00 device. Although the compatibility table explicitly states that the Agilex 5 supports the 00 device, it is not mentioned for the Arria 10; however, it seems likely to be compatible as well.
Thanks
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