Subject: [Arria 10 SoC] QSPI Flash Macronix Compatibility (MX66U2G45GXRI00)

1. Why the Distributor Recommended `MX66U2G45GXRI00` over `...54`

The distributor's recommendation is critical and correct:

* **`MX66U2G45GXRI54` ("54" Version):** Factory-configured with **Permanent 4 I/O (Permanent Quad Mode), Permanent 4-Byte Address Mode, and fixed dummy cycles (10 cycles)**.

* **`MX66U2G45GXRI00` ("00" Version):** The standard, backward-compatible version that powers up in **Standard SPI mode (1-bit / Single I/O)** and defaults to **3-Byte Address Mode**.

**Why this matters for Arria 10 HPS BootROM:**

The Arria 10 HPS BootROM **cannot boot from the "54" version**.

On cold boot / power-on reset, the Arria 10 HPS BootROM initializes the Cadence QSPI controller using hardcoded register defaults:

* Single I/O (1-bit data width, 1-bit address width)

* Standard 3-byte address mode (`numaddrbytes = 2` in the `devsz` register)

* Standard read opcode `0x03` (Normal Read) or `0x0B` (Fast Read)

Because the **"54"** version boots up with 1-bit SPI disabled (locked in Quad mode) and expects 4-byte addressing, the BootROM will fail immediately. The **`MX66U2G45GXRI00`** is mandatory because it powers on in standard 1-bit SPI mode with 3-byte addressing.

---

### 2. Arria 10 SoC BootROM & Architecture Compatibility

#### A. Misconception on SFDP in BootROM

Contrary to common belief, the **Arria 10 HPS BootROM does not parse JEDEC SFDP tables**.

The BootROM executes hardcoded, fixed-configuration read cycles. As long as the flash:

1. Powers up in standard 1-bit SPI (`0x03` or `0x0B` compatible).

2. Operates within the 1.8V power rail (`BSEL = 0x6`).

3. Responds to 3-byte addressing for the initial 16 MB memory window,

the BootROM will locate the boot header and load the U-Boot SPL / preloader into OCRAM.

#### B. The 2Gb (256MB) > 16MB Addressing Trap

Because this is a 2Gb device:

* The BootROM can only address the lower **16 MB (128 Mb)** of flash using standard 3-byte addresses.

* **Rule:** Your U-Boot SPL image must be located within the first 16 MB.

* Once U-Boot SPL takes control, the Cadence QSPI driver enters 4-byte address mode (`0x13` / `0x0C` opcodes or entering 4-byte mode via `0xB7`) to load U-Boot proper and the Linux kernel/FPGA bitstream from upper sectors.

* **Critical Warm Reset Requirement:** If the system undergoes a warm reset while the flash is left in 4-byte mode, the BootROM will crash upon reboot. Ensure your board ties the **HPS cold/warm reset to the hardware `RESET#` pin of the MX66U2G45G** (or enable soft-reset `0x66`/`0x99` handling) so the flash resets back to 3-byte default mode upon CPU reboot.