Release 26.3

Version: Release 26.3 PRO
Quartus Build/TAG: QPDS26.3 B114/QPDS26.3_REL_BASELINE_PR
Release Date: October 28, 2026
Device Affected: Agilex® 27 , Agilex® 3, Agilex® 5, Agilex® 7, N5X, Stratix® 10, Arria® 10
Release Type: Major release
Binary Release Path: http://releases.rocketboards.org/2026.10/
Release Page: https://github.com/altera-fpga/gsrd-socfpga/releases/tag/QPDS26.3_REL_BASELINE_PR

Major Features Released

• Simics Simulator support for Agilex® 27 device and System Example Design created.
  https://altera-fpga.github.io/rel-26.3/embedded-designs/agilex-27/common/virtual-platforms/linux-gsrd/ug-linux-gsrd-agilex27-virtual-platforms/
• System Example Design to support HPS AMP supporting configurations Linux + FreeRTOS, FreeRTOS+FreeRTOS for Agilex® 5.
  https://altera-fpga.github.io/rel-26.3/embedded-designs/agilex-5/e-series/premium-065a/amp_bao/ug-amp-bao-agx5e-premium-065a/
• Support of Ethernet in Nios V example for Agilex® 3 Atum A3 Nano dev kit using MSGDMA to connect with SDR SDRAM.
• Reference Design of a DisplayPort video output subsystem for use by the Application Processor for a Linux desktop display HMI use case for Agilex® 5.
• Improved BareMetal support raising the API abstraction level for Agilex® 5 and Agilex® 3. Support of USB3.1 for Agilex3 and Agilex5 in device mode.
  https://altera-fpga.github.io/rel-26.3/embedded-designs/agilex-5/e-series/premium-065a/baremetal/ug-baremetal-agx5e-premium-065a/
• Re-activated the Zephyr support including driver support of peripherals, examples and BSP generation for Agilex® 5 and Agilex® 3.
  https://altera-fpga.github.io/rel-26.3/embedded-designs/agilex-5/e-series/premium-065b/gsrd-zephyr/ug-zgsrd-agx5e-premium-065b/
  https://altera-fpga.github.io/rel-26.3/embedded-designs/agilex-5/common/virtual-platforms/zephyr-gsrd/ug-zephyr-gsrd-agilex5-virtual-platforms/
• Nios V Interfacing with Multi-Rate Ethernet PHY IP.
• Support of Use Case: mSGDMA IP in FPGA Fabric Connected to F2S bridge, via AXI security bridge (to allow ACE-Lite signals to be adjusted), SGDMA CSR's connected to H2F.
• HPS FreeRTOS Multicore Support for Agilex® 5.
• Support of Visual Design Studio (VDS) in all the Agilex® 7 System Example Designs.
• System Example Design for the Agilex® 5 Terasic DE25-Standard Board.
  https://altera-fpga.github.io/rel-26.3/embedded-designs/agilex-5/terasic/de25-standard/gsrd/ug-baseline-de25-standard/
• Support of Ubuntu running on HPS in Agilex® 5.
  https://altera-fpga.github.io/rel-26.3/embedded-designs/agilex-5/e-series/premium-065a/ubuntu/ug-ubuntu-agx5e-premium-065a/
• Support of Ubuntu running on HPS in Agilex® 5.
  https://altera-fpga.github.io/rel-26.3/embedded-designs/agilex-5/e-series/premium-065a/docker/ug-docker-agx5e-premium-065a/
• Integrate test-suit executable into Yocto recipe in so this get available as part of the Linux file system for Agilex® 5.
• System Example Design to demonstrate Time-Sensitive Networking (TSN) PHY configuration using RGMII from FPGA HVIO for the Agilex® 5 013B.
  https://altera-fpga.github.io/rel-26.1.1/embedded-designs/agilex-3/c-series/tsn/rgmii-hvio/ug-tsncfg2-agx3c-dk-rgmii-hvio/
• Support of Baseline System Example Design in Agilex® 7 devices.
• Support of Agilex® 7 HPS GSRD User Guide for I-Series FPGA Development Kit (rev D)
  https://altera-fpga.github.io/rel-26.3/embedded-designs/agilex-7/i-series/soc/gsrd-revd/ug-gsrd-agx7i-revd-soc/
• Cache Coherent Accelerator System Example Design for Agilex® 5.