Agilex5 - Bridge AXI F2H - read transactions
Hi, we are using in our design the bridge F2H between FPGA and HPS, which is a bus ACE5lite 256bits. Several masters AXI 64bits in our design will contact it via an interconnect. In Write, no problem, we can attaquer this interface in « narrow transfers » 64b over 256b, in conformity with ARM specification. But in READ, the SoC user manual (814346, 2026.01.09) says §11.5.1 : « The HPS F2H interface has a fixed data size of 256-bits. This interface allows for narrow burst sizes less than 256-bits However, if a fabric initiator generates a transfer narrower than the interface width (i.e., less than the 256-bits wide data and a nonzero burst size), there is no guarantee that the HPS F2H interface will respond with narrower data aligned on non-256-bit boundaries of the 256-bit data bus. For example, if ARADDR = 0x0010_0000, ARSIZE = 0x4, and ARLEN = 0x3, the HPS F2H interface returns two beats of 32 bytes per beat followed by two null cycles, instead of four beats of 16 bytes per beat. Altera recommends that you add width adaptation interconnect logic between the fabric initiator and the HPS F2H interface to ensure that the narrow-width data is packed/unpacked properly.” « the HPS F2H interface returns » : means it is sure that… , we will be able logic tranlation 256>64 considering that data returned on RDATA bus will fill all width of 256b (if enough read bytes of course). If “there is no guarantee…” is correct, it is a problem as there is no Read Strobe with bus RDATA in AXI spécification ; and we can not determine which bytes of which BEATs of transfert have to be considered. Last possible interpretation : the ‘width adaptation interconnect logic’ recommanded by Altera concerns more the transformation of ARADDR/ARSIZE/ARLEN by our interconnect at bridge input (AR* parameters are requests of read sent by our masters should be translated by interconnect before to be presented to bridge). Can you tell me the right meaning ? Thanks and regardsAgilex 5 Premium Dev Kit Ethernet Performance
Hello! We built the golden sample image following the HPS GSRD User Guide with additional packages to profile/evaluate the board and experience performance problems when sending data over ethernet. The test setup is a host connected to the dev kit and sending data to test the throughput. First, we used iperf3 with zero copy flag, which caps at about 940 Mbit/s with almost no variation. Without zero copy, iperf3 caps at about ~880 Mbit/s with some variation down to 629 Mbit/s, see attachment 1.png. With our custom application that also does some additional work, we’d expect about 430-440 Mbit/s, but cap at about 300 Mbit/s, with lots of time spent in kernel again, see attachment 2.png. From the first investigation, we suspect the driver can’t keep up with the generated data and can’t send it fast enough to the host. We are wondering whether we can adjust something in the kernel (driver) or in the image so that we can improve the throughput with heavy workloads. Kind regards!
Support Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA
Hi Altera Support Team, Greetings from Logic Fruit Technologies. This is Bhanu Pratap and I am working on the project in which we are using Agilex-7 SOC FPGA. Goal: Utilize Agiliex-HPS's capability on a Linux OS to control dynamic features of IP Cores at runtime. Problem Statement: We are facing an issue detecting SignalTap with SoC-based designs for runtime debugging while it's enabled and added from the Quartus project to generate the programming file. Brief Description: We are using Quartus 2025.1.1 and Altera's Agilex-7 Devkit(DKSIAAGI027FA: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit -> 4x F-Tile, Rev C). We downloaded the base GHRD design from Altera's GitHub webpage for the corresponding Quartus version. We are following each step to test GHRD and build generation for the Linux OS. We are using HPS First booting mode, we generated the build without modification and tested it. It's working fine according to the GSRD user guide. We have added a custom AXI4 Slave based CSR module to the HSP Lightweight bus to test basic register read/write using Platform Designer. We regenerated the build and re-tested but we are not getting the expected results so we added SignalTap for debugging. Build is generated using the STP file, programmed, and the OS is booting but it's not detecting SignalTap. This looks more like a process gap. We seek your support to fix this issue. Note: If we use an FPGA design without HPS, we are able to add and detect SignalTap. Seeking for urgent support. Thanks Bhanu Pratap
Release 25.3.1 PRO
Version: Release 25.3.1 PRO Quartus Build/TAG: B100/QPDS25.3.1_REL_GSRD_PR Release Date: January 16, 2026 Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7 Release Type: Major release/Binary release Binary Release Path: http://releases.rocketboards.org/2026.01/ Release Page: https://github.com/altera-fpga/gsrd-socfpga/releases/tag/QPDS25.3.1_REL_GSRD_PR Major Features Released Roll-your-own Linux GSRD 2.0 for Agilex™ 5 PDK OOBE DC on baseline design. Created the GSRD 2.0 rol-your-own Linux script for the Agilex™ 5 E-Series Premium DevKit with OOBE daughtercard for the GHRD 2.0 baseline design. Removed Legacy GSRD from Agilex™ 5 Premium Development kit + OOB Daughter card, keeping only Baseline (GSRD 2.0).
Agilex 5/3 FreeRTOS SMP Support
Stable Version: v25.4 Quartus Version: 25.4 Supported devices: Agilex™ 3 and Agilex™ 5 Source : https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v25.4-SMP Release Date: March 30, 2026 Hello Everyone, FreeRTOS port for A55/A76 HPS now supports SMP. visit the GitHub page for instructions on how to get started. Features and comments Features Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP (A55 x 2 or A76 x 2) Supported features Limitations/ Known issues A55 boot Yes Yes Yes Yes Single core boot, Dual core SMP A76 boot NA Yes NA Yes Single core boot, Dual core SMP QSPI boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes NAND boot No No No No Clk mngr driver Yes Yes Yes Yes API to get clock speed of different blocks Reset mngr driver Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory to memory transfer Only support memory to memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User defined and free running modes UART driver Yes Yes Yes Yes Full duplex Tx and Rx DMA not supported (Planned for future release I2C driver Yes Yes Yes Yes Master mode write and read Standard and fast modes DMA not supported (Planned for future release I3C driver Yes Yes Yes Yes Master mode write and read i3c and legacy i2c devices IBI not supported (Planned for future release) SPI driver Yes Yes Yes Yes Master mode write and read DMA is not supported QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase NAND driver No No No No SDM mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU enable support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes standard and HS speeds SDMMC and eMMC devices Fat FS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP and DHCP IPv4 and IPv6 support USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT diver Yes Yes Yes Yes interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver NT Yes NT Yes Enable, Disable Reboot mngr Yes Yes Yes Yes Warm/Cold reboot FPGA manager Yes Yes Yes Yes FPGA configuration Yes: Feature available and tested, No: Feature not available in SDK, NA : Not applicable , NT: Not tested Note: If you find any issues, please raise an issue in the GitHub page. For more support/assistance visit our website .
Agilex5 HPS2FPGA usage
Hello, I have an Agilex 5E 065B devkit board with Part Number A5ED065BB32AE6SR0. I have created a design in quartus that uses HPS2FPGA communication. I tested the design extensively and now want to configure the FPGA. However, it is not clear to me how the workflow has to be in that case after reading the documentation: https://docs.altera.com/r/docs/814550/current/agilextm-5-fpga-e-series-065b-premium-development-kit-user-guide/overview . Below I list my worklfow (which was not working out): Phase 1: Resotre GSRD I have a compiling quartus design I download the official GSRD JIC from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/ghrd_a5ed065bb32ae6sr0.hps.jic.tar.gz In quartus I open the JTAG programmer and connect the device to my local machine. I power on the device with SW27 set to OFF-OFF-OFF-OFF. After clicking "auto-detect", I right click my FPGA device and click "change file" and select the freshly downloaded jic file. I click "start" and wait till process is completed sccessfully. I insert the HPS board's SD card into my local machine and download the GSRD SD image from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/sdimage.tar.gz I rename the .wic file to a .img file. Then I use Win32DiskImager to flash the image to the SD card. After completion I insert the SD card back into the HPS board. I connect the vertical HPS board pin to my local machine and open PUTTY to target the COM port. A window opens, which stays blank. I set SW27 to OFF-ON-ON-OFF and power on the board. In PUTTY I can see the linux boot logs. I can log in as root without password. Phase 2: I download the U-BOOT hex that matches my device from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/u-boot-spl-dtb.hex I open a NIOS shell and create a .jic file based on my designs rbf, by typing the command: quartus_pfg -c <my_project>.sof <my_project>.jic -o device=MT25QU128 -o flash_loader=A5ED065BB32AR0 -o hps_path=<hex_file_path> -o mode=ASX4 -o hps=1 This created a .hps.jic file. I set SW27 back to OFF-OFF-OFF-OFF and connect to my local machine and power on the board. In quartus I again configure my newly created jic to the board via JTAG chain. After completion I power off the board and set SW27 back to OFF-ON-ON-OFF. I open a PUTTY window and power on the board. However, this time the PUTTY window stays quiet even after several minutes. So I guess the boot is not happening correctly. I would like to know if there is a substantial error in my workflow or, if there might be a problem in my quartus settings maybe (I have set configuration order to HPS first). I would be very glad if someone could help me with that. Feel free to tell me if any kind of log or additional information is required for understanding the error.
Preloader/U-Boot Compilation Failure
General Background: I'm working with a custom board that has an Altera/Intel Cyclone V, SoC FPGA (5CSEBA6U23, similar to the DE10-Nano development kit). The board is already equipped with all the necessary files for a successful boot sequence from a uSD card (FPGA and the ARM processor (HPS)). The Objective: I want to reconfigure the HPS functionality (Mux) for pins 53 and 54 from their current GPIO to CAN BUS. I need to ensure a successful boot from the uSD card with the updated hardware definition and Device Tree. Issue Description: Preloader/U-Boot Compilation Failure After successfully implementing the changes in Quartus and Platform Designer and after successfully generating the BSP files (bsp-editor), I'm attempting to run the "make" command to build the Preloader/U-Boot image. The process starts and creates the uboot-socfpga directory, but the compilation consistently fails with several errors, and the final boot image is not updated. Extension of the successfully completed steps: I've modified the Platform Designer (Qsys) mux functionality to reconfigure the HPS peripheral pins (GPIO53-GPIO54) for CAN BUS functionality. I've integrated the new HPS component into the top-level VHDL project. I've Generate a full VHDL compilation in Quartus. Using the "SoC EDS Command Shell", I launched the BSP-Editor and loaded the updated "settings.bsp" file. After generation, the "hps_isw_handoff" and "generated" directories were updated. I have manually verified the output files (pinmux_config.h) to confirms that CAN1 is now correctly configured in the pin multiplexing settings. What should I do?Agilex 5 HPS TEE
Hi, Is Arm Trust Zone supported on HPS? If so is the implementation of TEE supported on Agilex 5? I've checked TF-A sources and it seems that BL2 on this platform loads only BL31 and BL33. How about BL32? Is there an OP-TEE support? If not, are there any plans to provide it in the nearest feature?
Why does the system report an error when generating rbf from sof files and fsbl files?
Error message: Error: Internal Error: Sub-system: BITASM, File: /quartus/pgm/bitasm/bitasm_common_code.cpp, Line: 518 HPS data start address(-1950584) is not 16 aligned Device and tool information： The device used is Stratix 10 1SX110HN2F43I2VG, without using the Stratix 10 SoC Development Kit； Quartus Prime Pro25.1.1 U-boot source code：u-boot-socfpga-socfpga_v2025.04 ATF source code：arm-trusted-firmware-socfpga_v2.13.0 Operation steps： Simplified the Platform Designer section of the Stratix 10 GHRD project； 【Device and Pin Options】->【Configuration】Set the HPS/FPGA configuration order to be HPS First； The Quartus full compilation generates the sof file in the "output_files" directory； Compile the ATF source code, and obtain the bl31.bin file in the path of ./build/stratix10/release； Copy the bl31.bin file to the root directory of u-boot, compile the u-boot source code, and obtain the u-boot-spl file in the ./spl/ directory； Convert u-boot-spl to u-boot-spl.hex and copy it to the output_files directory； Open the Programming File Generator tool and configure the Output Files： Configure Input Files, add sof and HEX files： 9. Configuration Device： 10. Generate error：Why do I intermittently see reboot failure in the u-boot stage when running the Arria 10?
Hello, We are seeing intermittent failures in u-boot on warm reboot. U-Boot version: 2023.01Device: Arria10 To reproduce: Power on the system and let it boot. In the shell type the `reboot` command. U-boot gets stuck at the RAM ECC scrub stage (see output below). Reproducibility is about 50% of reboots. We have never seen this in a power on; we have only seen this on reboot during warm reboot (type the `reboot` command in the shell). U-boot only gets this far: U-Boot SPL 2023.01-26421-g0fa4e757b5-dirty (Jun 20 2023 - 00:59:09 +0000) U-Boot SPL 2023.01-26421-g0fa4e757b5-dirty (Jun 20 2023 - 00:59:09 +0000) DDRCAL: Success DDRCAL: Scrubbing ECC RAM (2048 MiB). This knowledge base article seems very relevant to this issue: https://community.altera.com/kb/knowledge-base/why-do-i-intermittently-see-reboot-failure-in-the-u-boot-stage-when-running-the-/339226 If so, is there a fix? Is that a fix in Quartus release as mentioned in the article? If so is there a release that fixes this issue? Is this a bug in the boot loader? If so, is there a version of the boot loader to fix this issue? Thank you!
