Hello,
Thank you all for your quick answers, I was finally able to make it work with the Ashlig RiscFree tool (only with ocr), the issue was on the installation of some of the linaro dependencies, since I'm working on Windows there were some errors during installation, but by manually installing the old toolchain in gcc-arm-8.3-2019.03-i686-mingw32-arm-eabi i was able to make it work.
Your are right about the wrong adress but I sent you with a typo, actually i was trying with ddr.
But now I'm facing another issue while running the Altera-SoCFPGA-HelloWorld-Baremetal-GNU example from HWLIBS, it works fine with ocr:
COMPILER ?= GNU
#COMPILER ?= ARMCC
#MEMORY ?= ddr
MEMORY ?= ocr
#SEMIHOSTED ?= 1
SEMIHOSTED ?= 0
HWLIBS_ROOT := C:/altera_pro/HWLIBS/msys64/home/work/intel-socfpga-hwlib/armv7a/hwlib
NEWLIB_ROOT := C:/intelFPGA/Toolchains/gcc-arm-8.3-2019.03-i686-mingw32-arm-eabi/arm-eabi
ADD_CFLAGS_GNU :=
ADD_CFLAGS_ARMCC :=
EXAMPLE_SRC := hello.c
ELF := application.axf
# These parameters can be overriden
# LINKER_SCRIPT
# HWLIBS_SRC
include Makefile.inc
But not when ddr is selected, while debugging with Ashling I see a lot of empty instructions like if the DDR was not accesible:
lowlevel_init:
10000000: andeq r0, r0, r0
10000004: andeq r0, r0, r0
10000008: andeq r0, r0, r0
1000000c: andeq r0, r0, r0
10000010: andeq r0, r0, r0
10000014: andeq r0, r0, r0
10000018: andeq r0, r0, r0
1000001c: andeq r0, r0, r0
_socfpga_main:
10000020: andeq r0, r0, r0
10000024: andeq r0, r0, r0
___mainCRTStartup_from_arm:
10000028: andeq r0, r0, r0
1000002c: andeq r0, r0, r0
_start:
10000030: ldr r3, [pc, #76] @ (0x10000080 <_start+80>)
10000032: cmp r3, #0
10000034: it eq
10000036: ldreq r3, [pc, #68] @ (0x1000007c <_start+76>)
10000038: mov sp, r3
1000003a: sub.w r10, r3, #65536 @ 0x10000
1000003e: movs r1, #0
Here I modified the start adress of the linker script to test others than the default but the same happened in 0x00100040
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
"elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_socfpga_main)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = 0x00100040;
.vector : { *(.vectors*) }
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
If I run the command bdinfo in uboot this is what I get:
=> bdinfo
boot_params = 0x00000100
DRAM bank = 0x00000000
-> start = 0x00000000
-> size = 0x40000000
flashstart = 0x00000000
flashsize = 0x00000000
flashoffset = 0x00000000
baudrate = 115200 bps
relocaddr = 0x3ff8b000
reloc off = 0x3ef8afc0
Build = 32-bit
current eth = ethernet@ff800000
ethaddr = (not set)
IP addr = <NULL>
fdt_blob = 0x3bf830d0
new_fdt = 0x3bf830d0
fdt_size = 0x00005e00
lmb_dump_all:
memory.cnt = 0x1
memory.size = 0x0
memory.reg[0x0].base = 0x0
.size = 0x40000000
reserved.cnt = 0x1
reserved.size = 0x0
reserved.reg[0x0].base = 0x3bf81ecc
.size = 0x407e134
arch_number = 0x00000000
TLB addr = 0x3fff0000
irq_sp = 0x3bf830c0
sp start = 0x3bf830b0
ARM frequency = 1200 MHz
DSP frequency = 0 MHz
DDR frequency = 0 MHz
Early malloc usage: 1544 / 2000
U-Boot SPL 2021.04 (Sep 02 2021 - 08:43:37 +0000)
FPGA: Checking FPGA configuration setting ...
FPGA: Start to program peripheral/full bitstream ...
FPGA: Early Release Succeeded.
U-Boot SPL 2021.04 (Sep 02 2021 - 08:43:37 +0000)
DDRCAL: Success
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 148 ms
FPGA: Checking FPGA configuration setting ...
FPGA: Skipping configuration ...
WDT: Started with servicing (10s timeout)
Trying to boot from MMC1
By this what I understand is that DDR was correctly initialized and from the original 0x0004_0000 - 0xC000_0000 SDRAM address, 0x0004_0000 - 0x3bf8_1ecc are available to run my code, but then in disassembly I see those empty instructions.
I'm using the precompiled uboot img in Arria10SoCGSRD following your reference, but this is prepared to configure the board to run a linux img not pure baremetal I guess.
Also that I don't understand is that when I use a direction outside that range in the linker script like 0x50000000 the Disassembly code makes sense and seems accesible:
lowlevel_init:
50000000: mrc 15, 0, r0, cr1, cr1, {2}
50000004: orr r0, r0, #3145728 @ 0x300000
50000008: mcr 15, 0, r0, cr1, cr1, {2}
5000000c: mov r0, #15728640 @ 0xf00000
50000010: mcr 15, 0, r0, cr1, cr0, {2}
50000014: mov r3, #1073741824 @ 0x40000000
50000018: vmsr fpexc, r3
5000001c: bx lr
_socfpga_main:
50000020: bl 0x50000000 <lowlevel_init>
50000024: b 0x50000028 <___mainCRTStartup_from_arm>
___mainCRTStartup_from_arm:
50000028: ldr pc, [pc, #-4] @ 0x5000002c <___mainCRTStartup_from_arm+4>
5000002c: andpl r0, r0, r1, lsr r0
_start:
50000030: ldr r3, [pc, #76] @ (0x50000080 <_start+80>)
50000032: cmp r3, #0
50000034: it eq
50000036: ldreq r3, [pc, #68] @ (0x5000007c <_start+76>)
50000038: mov sp, r3
But at the end I still getting an error which crashes the application and launch back uboot:
Hit any key to stop autoboot: 0 ////////////////(Here I stop manually and launch my code in Ashling ocr works ddr doesnt)
=> data abort
pc : [<5000363a>] lr : [<5000006d>]
reloc pc : [<1107d67a>] lr : [<1107a0ad>]
sp : 0007fff0 ip : 00000000 fp : 00000000
r10: 00070000 r9 : 3bf83eb0 r8 : 0000000a
r7 : 00000000 r6 : 00000001 r5 : 00000000 r4 : 50003784
r3 : 00000000 r2 : 00000000 r1 : 50003511 r0 : 00000000
Flags: nZCv IRQs off FIQs off Mode SVC_32 (T)
Code: f243 7484 f2c5 0400 (6825) f8d5
Resetting CPU ...
resetting ...
U-Boot SPL 2021.04 (Sep 02 2021 - 08:43:37 +0000)
Any hint?
New Contributor
