Hello,
Thank you all for your replies, I was finally able to make the HWLib example work Altera-SoCFPGA-HelloWorld-Baremetal-GNU (only with ocr) by downloading an old toolchain and using Ashlig apparently there was some error when installing linaro in windows and some dependencies were broken but still compiling without errors idk, and you were right about the address but it was a typo in the comment, I was using the other ddr.
But now I have some error when trying to run the example from the ddr instead of ocr:
XXX
COMPILER ?= GNU #COMPILER ?= ARMCC
MEMORY ?= ddr #MEMORY ?= ocr
#SEMIHOSTED ?= 1
SEMIHOSTED ?= 0
HWLIBS_ROOT := C:/altera_pro/HWLIBS/msys64/home/work/intel-socfpga-hwlib/armv7a/hwlib
NEWLIB_ROOT := C:/intelFPGA/Toolchains/gcc-arm-8.3-2019.03-i686-mingw32-arm-eabi/arm-eabi
ADD_CFLAGS_GNU :=
ADD_CFLAGS_ARMCC :=
EXAMPLE_SRC := hello.c
ELF := application.axf
# These parameters can be overridden
# LINKER_SCRIPT
# HWLIBS_SRC
include Makefile.inc
XXX
With ocr it works fine but with ddr it seems to aim to no accessible memory, because this is what I see in disassembly with default linker address:
XXX
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_socfpga_main)
/* Do we need any of these for elf? __DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = 0x00100040;
.vector : { *(.vectors*) }
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
}
XXX
It seems the memory is not accessible and obviously fails and launches uboot again:
XXX
lowlevel_init:
00100040: andeq r0, r0, r0
00100044: andeq r0, r0, r0
00100048: andeq r0, r0, r0
0010004c: andeq r0, r0, r0
00100050: andeq r0, r0, r0
00100054: andeq r0, r0, r0
00100058: andeq r0, r0, r0
0010005c: andeq r0, r0, r0
_socfpga_main:
00100060: andeq r0, r0, r0
00100064: andeq r0, r0, r0
___mainCRTStartup_from_arm:
00100068: andeq r0, r0, r0
0010006c: andeq r0, r0, r0
_start:
00100070: movs r0, r0
00100072: movs r0, r0
00100074: movs r0, r0
XXX
But from the uboot command:
XXX
=> bdinfo
boot_params = 0x00000100
DRAM bank = 0x00000000
-> start = 0x00000000
-> size = 0x40000000
flashstart = 0x00000000
flashsize = 0x00000000
flashoffset = 0x00000000
baudrate = 115200 bps
relocaddr = 0x3ff8b000
reloc off = 0x3ef8afc0
Build = 32-bit
current eth = ethernet@ff800000
ethaddr = (not set)
IP addr = <NULL>
fdt_blob = 0x3bf830d0
new_fdt = 0x3bf830d0
fdt_size = 0x00005e00
lmb_dump_all:
memory.cnt = 0x1
memory.size = 0x0
memory.reg[0x0].base = 0x0
.size = 0x40000000
reserved.cnt = 0x1
reserved.size = 0x0
reserved.reg[0x0].base = 0x3bf81ecc
.size = 0x407e134
arch_number = 0x00000000
TLB addr = 0x3fff0000
irq_sp = 0x3bf830c0
sp start = 0x3bf830b0
ARM frequency = 1200 MHz
DSP frequency = 0 MHz
DDR frequency = 0 MHz
Early malloc usage: 1544 / 2000
XXX
and shows SDRAM succed msg:
XXX
U-Boot SPL 2021.04 (Sep 02 2021 - 08:43:37 +0000)
FPGA: Checking FPGA configuration setting ...
FPGA: Start to program peripheral/full bitstream ...
FPGA: Early Release Succeeded.
U-Boot SPL 2021.04 (Sep 02 2021 - 08:43:37 +0000)
DDRCAL: Success
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 148 ms
FPGA: Checking FPGA configuration setting ...
FPGA: Skipping configuration ...
WDT: Started with servicing (10s timeout)
Trying to boot from MMC1
XXX
By this I understand that SDRAM was properly initialized and from the original 0x00040000 - 0xC0000000 available addresses, I can put my program in around 0x00040000 - 0x3bf00000 but as you see above it doesnt work and don't write the program properly.
Also i don't understand that if I modify the address to an outside of that range value like 0x50000000 it seems to write the correct data:
XXX
lowlevel_init:
50000000: mrc 15, 0, r0, cr1, cr1, {2}
50000004: orr r0, r0, #3145728 @ 0x300000
50000008: mcr 15, 0, r0, cr1, cr1, {2}
5000000c: mov r0, #15728640 @ 0xf00000
50000010: mcr 15, 0, r0, cr1, cr0, {2}
50000014: mov r3, #1073741824 @ 0x40000000
50000018: vmsr fpexc, r3
5000001c: bx lr
_socfpga_main:
50000020: bl 0x50000000 <lowlevel_init>
50000024: b 0x50000028 <___mainCRTStartup_from_arm>
___mainCRTStartup_from_arm:
50000028: ldr pc, [pc, #-4] @ 0x5000002c <___mainCRTStartup_from_arm+4>
5000002c: andpl r0, r0, r1, lsr r0
_start:
50000030: ldr r3, [pc, #76] @ (0x50000080 <_start+80>)
50000032: cmp r3, #0
50000034: it eq
50000036: ldreq r3, [pc, #68] @ (0x5000007c <_start+76>)
50000038: mov sp, r3
5000003a: sub.w r10, r3, #65536 @ 0x10000
XXX
But at the end the program crashes and launches back uboot:
XXX
Hit any key to stop autoboot: 0
///// here I launch the program with Ashling
=> data abort
pc : [<5000363a>] lr : [<5000006d>]
reloc pc : [<1107d67a>] lr : [<1107a0ad>]
sp : 0007fff0 ip : ffffffff fp : 00000000
r10: 00070000 r9 : 3bf83eb0 r8 : 3bf7ded0 r7 : 00000000
r6: 00000000 r5: 00000000 r4: 50003784
r3: 00000000 r2: 00000000 r1: 50003511 r0: 00000000
Flags: nZCv IRQs off FIQs off Mode SVC_32 (T)
Code: f243 7484 f2c5 0400 (6825) f8d5
Resetting CPU ...
resetting ...
U-Boot SPL 2021.04 (Sep 02 2021 - 08:43:37 +0000)
XXX
I am using the precompiled bootloader files following your reference in GSRD but I guess these are prepared for running only with the linux img and the SDRAM still not completely configured for baremetal? idk
Any clue?
New Contributor
