Agilex 5/3 FreeRTOS SDK Release
Stable Version: v26.1.1 Quartus Version: 26.1.1 Supported devices: Agilex™ 3 and Agilex™ 5 Source: https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v26.1.1 Release Date: October 9, 2026 Hello Everyone, A new version of the FreeRTOS SDK for Agilex 5/3 is now available. This release contains some fixes, along with UHS-1(SDR12/25/50) support for SD/eMMC. Visit the GitHub repository for instructions on how to get started. Features and Comments Feature Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP Supported Features Limitations / Known Issues A55 boot Yes Yes Yes Yes Single-core boot, Dual-core SMP, Quad-core SMP (Agilex 5) A76 boot NA Yes NA Yes Single-core boot, Dual-core SMP, Quad-core SMP QSPI boot Yes Yes Yes Yes eMMC boot NT Yes NT Yes SD boot NT Yes NT Yes NAND boot No No No No Clock Manager Yes Yes Yes Yes API to get clock speed of different blocks Reset Manager Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User-defined and free-running modes UART driver Yes Yes Yes Yes Full-duplex TX and RX I2C driver NT Yes NT Yes Master/Slave mode, standard and fast modes QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase I3C driver NT Yes NT Yes Master mode, I3C and legacy I2C devices SPI driver NT Yes NT Yes Master/Slave mode write and read NAND driver No No No No SDM Mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes Standard and HS HS, and UHS-I (SDR12/25/50) speeds, SDMMC and eMMC devices, FATFS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP, DHCP, IPv4 and IPv6 USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack Yes Yes Yes Yes USB mass storage operation WDT driver Yes Yes Yes Yes Interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver Yes Yes Yes Yes Enable/Disable bridges Reboot Manager Yes Yes Yes Yes Warm/Cold reboot FPGA Manager Yes Yes Yes Yes FPGA configuration Legend: Yes: Feature available and tested No: Feature not available in SDK NA: Not applicable NT: Not tested Note: If you find any issues, please raise an issue on the GitHub repository.
Introducing the Altera Community AI Responder — Beta
Altera is introducing the AI Responder, an assistant built into the Altera Community to help provide faster, context-aware guidance for Altera product questions. It uses relevant public Altera documentation and Knowledge Database content, with coverage continuing to expand. The AI Responder may provide source references and can hand off complex or out-of-scope questions to an Altera subject-matter expert. As a beta feature, responses may contain errors or omissions, so please review the sources and verify technical guidance against official Altera documentation before implementation. If the response does not fully address your question, add more context and tag ai_responder to continue the discussion. We welcome your feedback as we improve the Community experience.
Store custom keys on SDM Agilex3
Hi I know it's possible to store encryption and siging keys on the SDM for fpga firmware decryption and authentication, but is it possible to store my own keys on it? I will use the key to decrypt my own software files on the HPS, so I need some way to send the ecrypted software to the SDM then the SDM will use the key to decrypt it and send it back. Is there any documentation or tutorial for this?
Release 26.1.1
Version: Release 26.1.1 PRO Quartus Build/TAG: B130/QPDS26.1.1_REL_GSRD_PR Release Date: August 17, 2026 Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7, Startix® 10 Release Type: Major release/Binary release Binary Release Path: http://releases.rocketboards.org/2026.08/ Release Page: https://github.com/altera-fpga/gsrd-socfpga/releases/tag/QPDS26.1.1_REL_GSRD_PR Major Features Released Agilex™ 5 XEN Hypervisor 5 System Example Design https://altera-fpga.github.io/rel-26.1.1/virtualization/hypervisors/xen/ug-xen-agx5e-premium-065b/ , https://altera-fpga.github.io/rel-26.1.1/virtualization/hypervisors/xen/ug-xen-agx5e-premium-065a/ Agilex™ 5 RYO OPTE System Example Design Agilex™ 5 Quartus Reference Design using VDS Agilex™ 3 Time-Sensitive Networking (TSN): PHY configuration 2 (RGMII from FPGA HVIO) System Example Design Agilex™ 5 Performance Optimized Baseline SED support Agilex™ 5 DataMover / Bridge and Memory Benchmark System Example Design https://altera-fpga.github.io/rel-26.1.1/embedded-designs/agilex-5/e-series/premium-065a/data-mover/ug-data-mover-agx5e-premium-065a/ Agilex™ 3 support of FreeRTOS Agilex™ 5 Terasic DE25-Nano Board System Example DesignHow to Generate Altera HAL for HPS?
Hi, I am using Quartus 26.1 with the Agilex 5 Modular Development Kit (Device number: A5ED065BB32AE6SR0) and I have a few questions about BSP Generation for Hard Processor System (HPS). For reference I am following the Quartus Prime Pro Edition Version 26.1 User Guide. 1. How do I generate Altera HAL for HPS? When I use the BSP Editor in platform designer, I can only generate the system.h file that only has macros for EMIF, even though other peripherals are also connected to the HPS. How do I generate macros for the H2F bridges and HAL API Files for the HPS? 2. How do I input a SOPCINFO file into the BSP Editor? The Quartus Prime Pro Edition User Guide shows that I should be able to input SOPCINFO file as the system file (see above image) but Quartus only gives me the options of QSYS and IP file (see below image). Thank you for the help!Agilex 5/3 FreeRTOS SMP Support
Stable Version: v25.4 Quartus Version: 25.4 Supported devices: Agilex™ 3 and Agilex™ 5 Source : https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v25.4-SMP Release Date: March 30, 2026 Hello Everyone, FreeRTOS port for A55/A76 HPS now supports SMP. visit the GitHub page for instructions on how to get started. Features and comments Features Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP (A55 x 2 or A76 x 2) Supported features Limitations/ Known issues A55 boot Yes Yes Yes Yes Single core boot, Dual core SMP A76 boot NA Yes NA Yes Single core boot, Dual core SMP QSPI boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes NAND boot No No No No Clk mngr driver Yes Yes Yes Yes API to get clock speed of different blocks Reset mngr driver Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory to memory transfer Only support memory to memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User defined and free running modes UART driver Yes Yes Yes Yes Full duplex Tx and Rx DMA not supported (Planned for future release I2C driver Yes Yes Yes Yes Master mode write and read Standard and fast modes DMA not supported (Planned for future release I3C driver Yes Yes Yes Yes Master mode write and read i3c and legacy i2c devices IBI not supported (Planned for future release) SPI driver Yes Yes Yes Yes Master mode write and read DMA is not supported QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase NAND driver No No No No SDM mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU enable support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes standard and HS speeds SDMMC and eMMC devices Fat FS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP and DHCP IPv4 and IPv6 support USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT diver Yes Yes Yes Yes interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver NT Yes NT Yes Enable, Disable Reboot mngr Yes Yes Yes Yes Warm/Cold reboot FPGA manager Yes Yes Yes Yes FPGA configuration Yes: Feature available and tested, No: Feature not available in SDK, NA : Not applicable , NT: Not tested Note: If you find any issues, please raise an issue in the GitHub page. For more support/assistance visit our website .
Questions About Custom Linux Device Tree Handling in the Agilex 5 GSRD kas Build Environment
Hello, I have two questions regarding the following kas build environment: https://github.com/altera-fpga/agilex5e-ed-gsrd/tree/main/dk-a5e065bb32aea-enablement/baseline-a55/software/yocto_linux Custom Device Tree Application in FPGA Configuration First Mode My understanding is that FPGA_ENABLE_CORE_PGM, defined in kas.yml, is used to enable or disable FPGA core configuration from HPS, effectively selecting between HPS Boot First and FPGA Configuration First modes. However, when FPGA_ENABLE_CORE_PGM is set to 0 (FPGA Configuration First), I observed that the custom Linux Device Tree specified by CUSTOM_LINUX_DTS_FILE in machine.yml is not applied. After investigating the build flow, it appears that the kernel recipe (linux-socfpga-lts_%.bbappend) checks the value of FPGA_CORE_PGM_ENABLE (which corresponds to FPGA_ENABLE_CORE_PGM) to determine whether a custom Linux Device Tree should be applied. On the other hand, kas.yml also defines CUSTOM_LINUX_DEVICE_TREE, which seems to be the variable specifically intended to control custom Linux Device Tree usage. Therefore, I would have expected the kernel recipe to check CUSTOM_LINUX_DT (which corresponds to CUSTOM_LINUX_DEVICE_TREE) rather than FPGA_CORE_PGM_ENABLE. As an experiment, I made the following changes: 1) Modified the conditional check in the kernel recipe Before: FPGA_CORE_PGM_ENABLE After: CUSTOM_LINUX_DT 2) Set the following in kas.yml CUSTOM_LINUX_DEVICE_TREE = "1" With these changes, the custom Linux Device Tree was successfully applied even when using FPGA Configuration First mode. Could you please confirm whether the current implementation is intentional? If this behavior is by design, could you also explain the reason for using FPGA_CORE_PGM_ENABLE to determine whether a custom Linux Device Tree should be applied? Definition Location of CUSTOM_LINUX_DTS_FILE While reviewing the README located under: meta-custom/recipes-kernel/linux/device-tree/ I found the following statement: "FIT image - kernel.itb will use the custom device tree in CUSTOM_LINUX_DTS_FILE if defined in kas/bsp.yml, else it will use Linux Kernel in-tree device tree defined using LINUX_DTS_FILE in kas/bsp.yml." However, I observed that defining CUSTOM_LINUX_DTS_FILE in kas/bsp.yml does not seem to have any effect. After further investigation, I noticed that CUSTOM_LINUX_DTS_FILE is already defined by default in kas/machine.yml, and it appears that the value from machine.yml is actually being used. In addition, LINUX_DTS_FILE is also defined by default in kas/machine.yml. Based on these observations, I am wondering whether the README might contain a typo, and that the references to kas/bsp.yml should actually be kas/machine.yml. Could you please confirm whether this understanding is correct? Thank you for your time and support.Agilex 5E HPS and Linux
Hi. 1. Is there a simple method to run two Linux systems on HPS, i.e.: Linux 1 - 2xA55 and Linux 2 - 2xA76 with different sets of peripherals? 2. Is it possible to use one Ethernet port by these two Linux systems. 3. Is there a simple method for communication between these two Linux systems?
Agilex 3 Baremetal example
We need to be able to run the Agilex 3 as baremetal We tried to re-target this Agilx5 baremetal tutorial: Baremetal Hello World Example for Agilex™ 5 Premium To be used on Altera's Agilex 3 EVB : GitHub - altera-fpga/agilex3c-ed-gsrd: Altera Agilex 3 C-series GSRD · GitHub but this seems to be too great of a task for us - everything there is custom made for the Agilex 5 Please help.
