HPS ip configuration in platform designer for uart0 enabling in arria 10 soc

Hi Essen,

Have you reviewed the Arria 10 Golden System Reference Design: 

https://altera-fpga.github.io/rel-26.1/embedded-designs/arria-10/sx/soc/gsrd/ug-gsrd-a10sx-soc/

Sue

Hi Essen​ , 

If your Platform Designer configuration has UART0 enabled and routed to the dedicated HPS I/O pins, you are on the right track for the hardware side. Ensure you have generated the system and compiled the hardware project to get the .sof file and the handoff files.

For the software side, developing a bare-metal application on Windows without involving Linux is fully supported using the SoC EDS Embedded Command Shell and the Altera HWLIBs.

Here is the step-by-step workflow to get your "Hello World" running over UART0:

1. The Bare-Metal C Application Reference

You do not need to write this from scratch. You can find the official bare-metal "Hello World" examples in the Altera Open Source GitHub repository here: https://github.com/altera-opensource/intel-socfpga-hwlib/tree/master/examples/A10

Note: Since you mentioned using the Linaro Bare-Metal Toolchain, make sure you look at the Altera-SoCFPGA-HelloWorld-Baremetal-GNU example, rather than the ARMCC version, so your Makefile aligns with the GCC compiler.

In the main.c of that example, the core logic relies on #include "alt_uart.h" and #include "alt_clock_manager.h". It handles initializing the clock, initializing the UART0 instance, setting the baud rate (115200), and using alt_printf() or alt_uart_write() to output the string.

2. Building/Compiling with the Linaro Toolchain

To build this in Windows:

Open the SoC EDS Embedded Command Shell (run Embedded_Command_Shell.bat from your SoC EDS installation folder). This environment automatically sets up the paths for the Linaro arm-none-eabi-gcc compiler.

Navigate to your downloaded Altera-SoCFPGA-HelloWorld-Baremetal-GNU directory.

Run the make command. This will compile your .c files, link them against the HWLIBs, and generate an .axf (or .elf) executable file.

3. Generating Boot Files (For SD Card/Flash Boot)

If you intend to boot this application standalone from hardware (instead of debugging via JTAG):

Use the bsp-editor to generate the U-Boot SPL (Preloader) from your Quartus hardware handoff folder.

Compile the Preloader using the Command Shell.

Use mkimage (available in the EDS shell) to wrap your compiled binary with a U-Boot header, creating an .img or .scr script that U-Boot can execute to jump to your bare-metal entry point.

4. Loading and Running on the Target Device (JTAG Approach)

For initial bare-metal development, it is much faster to load and run the code directly into RAM via JTAG using ARM Development Studio (ARM DS), which is bundled with SoC EDS.

Connect your Intel FPGA Download Cable (USB Blaster) to the Arria 10 board.

Open ARM DS and create a new Debug Configuration.

Select the target as Arria 10 SoC and connect via the USB Blaster.

Point the debugger to your compiled .axf file.

ARM DS will load the executable directly into the HPS RAM via JTAG and halt at main().

Try pulling down the GNU example from the GitHub repository and compiling it in the SoC EDS shell. Let us know if you hit any roadblocks during the build phase.