Forum Discussion
Occasional ContributorReg SoC Example without using Linux
Team,
Just want to understand do we have any SoC example or steps for implementing SoC without using Linux, as customer is Xilinx legacy user and they are implementing and running System-on-Chip (SoC) on a Xilinx FPGA without using Linux.
Regards
amolkumar
5 Replies
RaduB_AlteraHello,
The existing bare-metal library for Agilex 5 was discontinued.
Altera plans to introduce an improved bare-metal library in the 26.3 release, offering broader functionality and greater ease of use. We recommend waiting for this release before starting a new bare-metal project for Agilex 5.
Thank you,
Radu
umut_arrowYou can run RTOS (Zephyr or FreeRTOS) or Baremetal on an SoC-FPGA. There are handful of reference designs on Github, as well as the GHRD which you can strip down. I put some links below.
Are you looking at any specific device family?https://altera-fpga.github.io/rel-25.1/driver-list_zephyr/
https://altera-fpga.github.io/rel-25.1/driver-list_baremetal/
amolkumarThnaks for update.
Can you suggest links for design except for Hello world for Agilex5 or Cyclone V
Regards
amol
- umut_arrow
I'm assuming you're interested in baremetal rather than Zephyr.
There is no other "full-on" reference designs other than Hello World example as far as I know. But, the example includes all the necessary peripherals (UART, I2C, SPIO, GPIO, etc.). Take a look at the included and source folders in the Github repo https://github.com/altera-fpga/baremetal-driversFor Cyclone V, take a look at the AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit. This devkit comes with a project/software that you can run baremetal.
https://www.rocketboards.org/foswiki/Documentation/HWLib
There are also a healthy amount of third-party reference designs you can find online. Take a look at one from Cornell University below it goes through Cyclone V HPS baremetal. I'd look at Cornell's ECE5760 Course page. They do a lot of stuff with DE1-SoC and DE10-Nano boards. It's all available online.
https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/SoC-FPGA%20Design%20Guide_EPFL.pdf
sonycmanNew Contributor
Tried that baremetal helloworld example design recently on agilex 5 board, and got very strange feelings about it.
My UART does not even working in it, because the code assumes its clock should be stable 100 Mhz, but the chip run on bare inaccurate onchip oscillator (150 - 300 Mhz).
Are you guys forget to setup PLLs?
