F2SDRAM test inquiries.

Hi Guys,

I am testing the F2SDRAM bridge. 32 bit address, 256bits data. 

Due to recurring missing Verilog file errors for the Qsys adapter IP whenever switching PCs, I removed the adapter earlier and am currently testing by directly exporting f2s from the HPS to the top level.

I implemented tester logic on the FPGA side to write and read 256-bit data once per transaction (len=0) for 2048 comparisons, but the B channel signal keeps returning 2'b11 (DECERR).

I implemented the tester logic on the FPGA side to perform 2,048 read/write comparison cycles with 256-bit data in single-beat transactions (len=0) using a base address of 0x8000_0000. However, I am at a loss because the B channel signal continuously returns 2'b11 (DECERR).

Debugging this solely based on the B channel response is quite challenging. For reference, I am currently running this test on an 013b devkit using the GHRD Linux Reference Design, triggering the start signal via Signal Probe after the kernel has fully booted up

Could this be an issue with sideband signals or the kernel driver? Gemini suggests that the bridge might be in reset or it could be due to SMMU. I have already disabled SMMU.

As expected, learning and applying new technology is always tough.

Thank.