F2SDRAM test inquiries.

Hi HPark14,

Thanks for the details and screenshots.

Looking at your Signal Tap capture and RTL connections, one item stands out: AWUSER / ARUSER are tied to 8'd0.

For Agilex 5 F2SDRAM, the HPS TRM (Sec 12.2.6.3 AxUSER Bit Connectivity) states that fabric accesses through F2SDRAM should use AxUSER[7:0] = 0xE0.

https://docs.altera.com/r/docs/814346/26.1/hard-processor-system-technical-reference-manual-agilex-5-socs/axuser-bit-connectivity

The Platform Designer f2sdram_adapter IP is also typically placed in front of the f2sdram bridge to decorate AXI transactions, so they are routed and managed properly within the HPS.

https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/documentation/09_menu_p_hw_f2sdram_bridge.md

Suggested next step:

Please try either:

assign awuser = 8'hE0;

assign aruser = 8'hE0;

or re-instantiate the f2sdram_adapter between your tester and f2sdram_axi4_sub, then re-check BRESP in Signal Tap.

Thanks,

Lok