Need Step-by-Step Guide: Configuring Arria 10 HPS for UART0 Access (Tools & Workflow)
Hello Altera Community, I am starting a new project using the Intel/Altera Arria 10 SoC FPGA. My immediate goal is to successfully configure the Hard Processor System (HPS) side of the chip and enable HPS UART0 access so I can view the boot messages and interact via a serial console terminal. Since I am new to the Arria 10 HPS ecosystem, could someone provide a detailed, step-by-step workflow of the procedure? Specifically, I would appreciate guidance on: 1. Required Tools: Which exact software versions (Quartus Prime Pro, SoC EDS, Arm DS, etc.) are recommended for a stable Arria 10 HPS development pipeline? 2. Platform Designer (Qsys) Setup: What are the specific steps to route and configure UART0 pins, clocks, and DDR parameters inside Platform Designer? 3. Bootloader Generation: How do I correctly handle the hardware handoff files to generate the U-Boot/SPL bootloader using the SoC EDS utilities? 4. Target OS: I intend to use Bare-Metal . What are the final steps to write these images to a boot medium (like an SD card / QSPI flash) to verify that UART0 is transmitting successfully? If there are any updated Golden System Reference Designs (GSRD), specific user guides, or community tutorials that outline this exact UART0 baseline setup, please share the links. Thank you in advance for your time and guidance! Best regards, Team D&D ESSEN
Agilex7m i have configure 4GB ddr linux is not booting. I got architect time failure error.
Agilex7m I have configure 2GB DDR, linux is booting fine. But if I configure 4GB ddr linux is not booting. I got architect time failure error. But 2GB ddr configuration this error not came. I u-boot 4GB ddr is accessible but linux is not booting Boot logs init_mem_cal: Initial DDR calibration IO96B_0 succeed DDR: Calibration success is_mailbox_spec_compatible: IOSSM mailbox version: 1 DDR5: 4096 MiB ecc_interrupt_status: ECC error number detected on IO96B_0: 0 DDR5: size check success DDR5: firewall init success DDR5 init success QSPI: Reference clock at 500000 kHz Trying to boot from SPI Board ID is not in range 0 to 255 ## Checking hash(es) for config board-0 ... OK ## Checking hash(es) for Image atf ... crc32+ OK ## Checking hash(es) for Image uboot ... crc32+ OK ## Checking hash(es) for Image fdt-0 ... crc32+ OK NOTICE: BL31: v2.13.1(release):QPDS25.3.1_REL_GSRD_PR NOTICE: BL31: Built : 10:40:22, Nov 25 2025 U-Boot 2025.10-ga0db71cfad37-dirty (Dec 11 2025 - 10:49:42 +0000)socfpga_agilex7m CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53) Model: SoCFPGA Agilex7-M SoCDK DRAM: 2 GiB (total 4 GiB) Core: 38 devices, 22 uclasses, devicetree: separate NAND: 0 MiB MMC: mmc@ff808000: 0 Loading Environment from FAT... OK In: serial@ffc02000 Out: serial@ffc02000 Err: serial@ffc02000 Board ID is not in range 0 to 255 Net: eth0: ethernet@ff800000 Hit any key to stop autoboot: 0 SOCFPGA_AGILEX7M # SOCFPGA_AGILEX7M # SOCFPGA_AGILEX7M # SOCFPGA_AGILEX7M # bdinfo boot_params = 0x0000000000000100 DRAM bank = 0x0000000000000000 -> start = 0x0000000000000000 -> size = 0x0000000080000000 DRAM bank = 0x0000000000000001 -> start = 0x0000000100000000 -> size = 0x0000000080000000 flashstart = 0x0000000000000000 flashsize = 0x0000000000000000 flashoffset = 0x0000000000000000 baudrate = 115200 bps00 8N1 | NOR | Minicom 2.9 | VT102 | Offline | ttyACM0 relocaddr = 0x000000007fee9000 reloc off = 0x000000007fce9000 Build = 64-bit current eth = ethernet@ff800000 ethaddr = b6:97:a4:21:e2:4a IP addr = 169.254.65.121 fdt_blob = 0x000000007fae1950 lmb_dump_all: memory.count = 0x2 memory[0] [0x0-0x7fffffff], 0x80000000 bytes, flags: none memory[1] [0x100000000-0x17fffffff], 0x80000000 bytes, flags: none reserved.count = 0x3 reserved[0] [0x0-0x1ffffff], 0x2000000 bytes, flags: no-map reserved[1] [0x7eae1940-0x7fffffff], 0x151e6c0 bytes, flags: no-overwrite reserved[2] [0x17fff7000-0x17fffffff], 0x9000 bytes, flags: no-notify, no-overwrite devicetree = separate serial addr = 0x00000000ffc02000 width = 0x0000000000000004 shift = 0x0000000000000002 offset = 0x0000000000000000 clock = 0x0000000005f5e100 arch_number = 0x0000000000000000 TLB addr = 0x000000007ffe0000 irq_sp = 0x000000007fae1940 sp start = 0x000000007fae1940 Early malloc usage: 1608 / 2000 Failure log: init_mem_cal: Initial DDR calibration IO96B_0 succeed DDR: Calibration success is_mailbox_spec_compatible: IOSSM mailbox version: 1 DDR5: 4096 MiB ecc_interrupt_status: ECC error number detected on IO96B_0: 0 DDR5: size check success DDR5: firewall init success DDR5 init success QSPI: Reference clock at 500000 kHz Trying to boot from SPI Error: -22 Trying to boot from MMC1 Board ID is not in range 0 to 255 ## Checking hash(es) for config board-0 ... OK ## Checking hash(es) for Image atf ... crc32+ OK ## Checking hash(es) for Image uboot ... crc32+ OK ## Checking hash(es) for Image fdt-0 ... crc32+ OK NOTICE: BL31: v2.13.1(release):QPDS25.3.1_REL_GSRD_PR NOTICE: BL31: Built : 10:40:22, Nov 25 2025 U-Boot 2025.10 (Dec 11 2025 - 10:49:42 +0000)socfpga_agilex7m CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53) Model: SoCFPGA Agilex7-M SoCDK DRAM: 2 GiB (total 4 GiB) Core: 38 devices, 22 uclasses, devicetree: separate NAND: 0 MiB MMC: mmc@ff808000: 0 Loading Environment from FAT... OK In: serial@ffc02000 Out: serial@ffc02000 Err: serial@ffc02000 Board ID is not in range 0 to 255 Net: eth0: ethernet@ff800000 Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0(part 0) is current device Scanning mmc 0:1... Found U-Boot script /boot.scr.uimg 2411 bytes read in 3 ms (784.2 KiB/s) ## Executing script at 05ff0000 crc32+ Trying to boot Linux from device mmc0 Found kernel in mmc0 13661579 bytes read in 979 ms (13.3 MiB/s) ## Loading kernel (any) from FIT Image at 02000000 ... Using 'board-0' configuration Verifying Hash Integrity ... OK Trying 'kernel' kernel subimage Description: Linux Kernel Type: Kernel Image Compression: lzma compressed Data Start: 0x020000dc Data Size: 10439444 Bytes = 10 MiB Architecture: AArch64 OS: Linux Load Address: 0x06000000 Entry Point: 0x06000000 Hash algo: crc32 Hash value: 0ccd8e20 Verifying Hash Integrity ... crc32+ OK ## Loading fdt (any) from FIT Image at 02000000 ... Using 'board-0' configuration Verifying Hash Integrity ... OK Trying 'fdt-0' fdt subimage Description: socfpga_socdk_vanilla Type: Flat Device Tree Compression: uncompressed Data Start: 0x029f4cd4 Data Size: 32121 Bytes = 31.4 KiB Architecture: AArch64 Hash algo: crc32 Hash value: 262d6a47 Verifying Hash Integrity ... crc32+ OK Booting using the fdt blob at 0x29f4cd4 Working FDT set to 29f4cd4 Uncompressing Kernel Image to 6000000 Loading Device Tree to 000000007ead6000, end 000000007eae0d78 ... OK Working FDT set to 7ead6000 SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB Enabling QSPI at Linux DTB... Working FDT set to 7ead6000 libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND QSPI clock frequency updated RSU: Firmware or flash content not supporting RSU RSU: Firmware or flash content not supporting RSU RSU: Firmware or flash content not supporting RSU RSU: Firmware or flash content not supporting RSU Starting kernel ... Deasserting all peripheral resets [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Linux version 6.12.43-altera-gd16fc609d5a7 (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 14.3.0, GNU ld (GNU Binutils) 2.44.0.20250715) #1 SMP PREEMPT Tue Nov 25 16:06 :07 UTC 2025 [ 0.000000] KASLR disabled due to lack of seed [ 0.000000] Machine model: SoCFPGA Agilex7-M SoCDK [ 0.000000] efi: UEFI not found. [ 0.000000] earlycon: uart0 at MMIO32 0x00000000ffc02000 (options '115200n8') [ 0.000000] printk: legacy bootconsole [uart0] enabled [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000000000000, size 32 MiB [ 0.000000] OF: reserved mem: initialized node svcbuffer@0, compatible id shared-dma-pool [ 0.000000] OF: reserved mem: 0x0000000000000000..0x0000000001ffffff (32768 KiB) nomap non-reusable svcbuffer@0 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x000000017fffffff] [ 0.000000] NODE_DATA(0) allocated [mem 0x17f7fbe80-0x17f7fe4bf] [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000000000000-0x00000000ffffffff] [ 0.000000] DMA32 empty [ 0.000000] Normal [mem 0x0000000100000000-0x000000017fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000001ffffff] [ 0.000000] node 0: [mem 0x0000000002000000-0x000000007fffffff] [ 0.000000] node 0: [mem 0x0000000100000000-0x000000017fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000017fffffff] [ 0.000000] cma: Reserved 32 MiB at 0x000000007ca00000 on node -1 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.5 [ 0.000000] percpu: Embedded 25 pages/cpu s61784 r8192 d32424 u102400 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: ARM erratum 845719 [ 0.000000] alternatives: applying boot alternatives [ 0.000000] Kernel command line: earlycon panic=-1 root=/dev/mmcblk0p2 rw rootwait [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) [ 0.000000] Fallback order for Node 0: 0 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1048576 [ 0.000000] Policy zone: Normal [ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off [ 0.000000] software IO TLB: area num 4. [ 0.000000] software IO TLB: mapped [mem 0x0000000078a00000-0x000000007ca00000] (64MB) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 [ 0.000000] rcu: Preemptible hierarchical RCU implementation. [ 0.000000] rcu: RCU event tracing is enabled. [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=4. [ 0.000000] Trampoline variant of Tasks RCU enabled. [ 0.000000] Tracing variant of Tasks RCU enabled. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 [ 0.000000] RCU Tasks: Setting shift to 2 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=4. [ 0.000000] RCU Tasks Trace: Setting shift to 2 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=4. [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. [ 0.000000] timer_probe: no matching timers found [ 0.000000] Kernel panic - not syncing: Unable to initialise architected timer. [ 0.000000] CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 6.12.43-altera-gd16fc609d5a7 #1 [ 0.000000] Hardware name: SoCFPGA Agilex7-M SoCDK (DT) [ 0.000000] Call trace: [ 0.000000] dump_backtrace.part.0+0xd4/0xe0 [ 0.000000] show_stack+0x18/0x30 [ 0.000000] dump_stack_lvl+0x60/0x80 [ 0.000000] dump_stack+0x18/0x24 [ 0.000000] panic+0x168/0x360 [ 0.000000] time_init+0x30/0x50 [ 0.000000] start_kernel+0x544/0x6d0 [ 0.000000] __primary_switched+0x80/0x88
Support Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA
Hi Altera Support Team, Greetings from Logic Fruit Technologies. This is Bhanu Pratap and I am working on the project in which we are using Agilex-7 SOC FPGA. Goal: Utilize Agiliex-HPS's capability on a Linux OS to control dynamic features of IP Cores at runtime. Problem Statement: We are facing an issue detecting SignalTap with SoC-based designs for runtime debugging while it's enabled and added from the Quartus project to generate the programming file. Brief Description: We are using Quartus 2025.1.1 and Altera's Agilex-7 Devkit(DKSIAAGI027FA: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit -> 4x F-Tile, Rev C). We downloaded the base GHRD design from Altera's GitHub webpage for the corresponding Quartus version. We are following each step to test GHRD and build generation for the Linux OS. We are using HPS First booting mode, we generated the build without modification and tested it. It's working fine according to the GSRD user guide. We have added a custom AXI4 Slave based CSR module to the HSP Lightweight bus to test basic register read/write using Platform Designer. We regenerated the build and re-tested but we are not getting the expected results so we added SignalTap for debugging. Build is generated using the STP file, programmed, and the OS is booting but it's not detecting SignalTap. This looks more like a process gap. We seek your support to fix this issue. Note: If we use an FPGA design without HPS, we are able to add and detect SignalTap. Seeking for urgent support. Thanks Bhanu PratapS10 hps fpga2sdram bridge low speed
Hello, i have some problems I have a project with stratix 10 with hps I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width Via u-boot smc configured and enabled them, but measured speed is not enough. When I use onle one bridge my speed is approximately 32 gbit/s (bridge and master frequency 350 MHz) But when I use all 3 bridges it becomes 20 gbit/s I use avmm bridge to connect to axi fpga2sdram bridge with 128 bits width, max pending writes 16, max burst size 128, use only write to bridge ECC in emif (hmc) is disabled I tried to use QoS for bridges, set them to bypass P.S. If i use the same board with firmware without hps, i get 130 gbit/s (with disabled hps) Quartus Pro 21.4 Any help would be useful!
Agilex 5 Premium Dev Kit Ethernet Performance
Hello! We built the golden sample image following the HPS GSRD User Guide with additional packages to profile/evaluate the board and experience performance problems when sending data over ethernet. The test setup is a host connected to the dev kit and sending data to test the throughput. First, we used iperf3 with zero copy flag, which caps at about 940 Mbit/s with almost no variation. Without zero copy, iperf3 caps at about ~880 Mbit/s with some variation down to 629 Mbit/s, see attachment 1.png. With our custom application that also does some additional work, we’d expect about 430-440 Mbit/s, but cap at about 300 Mbit/s, with lots of time spent in kernel again, see attachment 2.png. From the first investigation, we suspect the driver can’t keep up with the generated data and can’t send it fast enough to the host. We are wondering whether we can adjust something in the kernel (driver) or in the image so that we can improve the throughput with heavy workloads. Kind regards!Agilex 5 with HPS
Hi, I have a question regarding Agilex 5 with HPS. I intend to deliver to the client a device based on Agilex 5 and HPS, but initially the HPS must remain fully offline. In other words, once the device is shipped, I need to ensure with 100% certainty that no software or program can be executed on the HPS, and that there is no possible way for the client to interact with or enable it prematurely. At the same time, I need to retain the ability to remotely deploy a new FPGA bitstream at a later stage, which will enable the HPS once the HPS software development is completed. Is such a workflow achievable on this platform?
