LWH2F Throughput
Dear all, I'm facing the issue that the throughput on the Agilex 5 LWH2F interface appears to be lower compared to Cyclone 5. - I have two custom boards, one is based on Cyclone 5, the other on Agilex 5. - I use a linux OS. The code runs in a linux kernel driver. The code for the driver is the same for both devices. - The memory is mapped using ioremap(), i.e. it is mapped as device memory. - I measure performance by taking a timestamp with ktime_get_ns(), then read/write 10000 uint32 values, then take another timestamp. - I've measured the follwing values - Cyclone5 board read: 47.2 MB/s (million bytes per second or 11.8 million words à 4 byte per second) - Cyclone5 board write: 73.1 MB/s - Agilex5 board read: 24.8 MB/s - Agilex5 board write: 18.8 MB/s - I've noticed that performance varies, depending on the CPU that the process is running on (when measuring in userspace I can explicitly set the cpu affinity; For the kernel driver I've noticed that it is sometimes slower than above, presumably because it's running on a different cpu). - There is a slight difference in the QSYS design: - The Cyclone5 based board: - drives the AXI bus with a 64 MHz clock. - uses the Avalon MM Slave Translator. - The Agilex5 based board: - drives the AXI bus with a 200 MHz clock. - uses the Avalon Memory Mapped Pipeline Bridge Intel FPGA IP. - Our FPGA takes one 64/200 MHz cycle to process the read (readdatavalid). For a write our FPGA doesn't generate a writeresponsevalid, this is handled by the IP block. - I'm using Quartus 25.1.1 for the Agilex 5 design. I'm aware that the LWH2F interface is not intended for high throughput. Also, since the memory is mapped as "Device Memory", every load/store is processed separately and we're not taking advantage of AXI bursts, etc. I'm aware that we could improve performance by using the H2F interface and mapping the memory as normal memory. That said, we have a prooven design and are reluctant to change it unless absolutely neccessary. So I have the following questions: - Is a higher latency expected on Agilex5? (E.g. due to a different architecture of the interconnect) - Have you measured the performance of the LWH2F interface? Can you give me a number on how many transactions per second we can expect? Kind Regards, Eric Opitz
Stratix 10 HPS 8GB SODIMM shared memory for HPS and FPGA
We have custom board with stratix 10 FPGA. the HPS boots from 8GB eMMC and teh linux runs of 2GB soldered DDR4. We also have a 8GB DDR4 SODIMM which we plan to use as a shared memory between the HPS and FPGA. We need help in interfacing this memory with the HPS and FPGA. There are about 8 FPGA modules that need to access the SODIMM along with teh HPS. So total of 8 ports to the memory controller. Can you suggest a solution for this. Is there any muti port wrapper ip for the EMI IP which we can use for this. Also, can the HPS h2f bridge access 8GB memory?
Stratix 10 Linux SD card booting
Hi Altera Community, I tried multiple attempts to boot the SD card from Rocketboard.org. https://releases.rocketboards.org/ I downloaded and booted the SD card with the .wic image file. It only has the .itb file by default in the boot partition. Whenever I try to boot, it asks for the U-Boot.img file. And also it says "failed to load "socfpga_stratix10_socdk.dtb" even if the file is there. And then I compiled my simple HPS design and can easily program the FPGA from the Quartus Programmer (rbf and sof file), but whenever I try to overlay it, like say: echo overlay.dtb > /sys/kernel?config?device-tree/overlays/0/path It says "FPGA manager error, timeout," and so on. Does any community member have notes or steps that you made to boot the SD card of the Stratix 10 FPGA? I am following this link: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderStratix10F2SDRAM fails to synthesize with custom logic
Hello guys, We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-level ports. Does anyone know why this is happening? Also, is there an example design for F2SDRAM available? The GHRD is not very helpful since it only includes the JTAG master. I suspect it might be a design issue, so I even removed the adapter and connected it only within Qsys, but it’s still acting up like this. Does anyone know why this is happening even though everything is clearly declared and connected? Hudson
TSE -> SGDMA -> SOC(through f2sdram)
Hi, I'm trying to transfer an old design with multiple TSEs / SGMDAs and a NIOS to a newer Agilex 5. We are also evaluating the use of the SOC instead of the NIOS in the design. I've made a minimized platform design for it but it fails during synthesis with the notorious error for the f2sdram bus: There is both a 'memory -> streaming' and 'streaming -> memory' sgdma in the design present, so both read and write port on the axi bus should be present. If I connect the SGDMA's to the fpga2hps bus the same error is generated. Are there settings in the SGDMAs that needs to be set to a certain value so that the correct read/write avalon MM/AXI interface is generated?
HPS ip configuration in platform designer for uart0 enabling in arria 10 soc
I have software tools Quartus prime pro 26.1, soc eds 20.1 and linaro baremetal tool chain. Now i configure the HPs ip for uart0 enabling but i am not sure wether it is correct or not, can you please conform it, and guide if there any changes required and if configuration is fine tell me the next steps to do. Regards Tean D&D, ESSENS10 hps fpga2sdram bridge low speed
Hello, i have some problems I have a project with stratix 10 with hps I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width Via u-boot smc configured and enabled them, but measured speed is not enough. When I use onle one bridge my speed is approximately 32 gbit/s (bridge and master frequency 350 MHz) But when I use all 3 bridges it becomes 20 gbit/s I use avmm bridge to connect to axi fpga2sdram bridge with 128 bits width, max pending writes 16, max burst size 128, use only write to bridge ECC in emif (hmc) is disabled I tried to use QoS for bridges, set them to bypass P.S. If i use the same board with firmware without hps, i get 130 gbit/s (with disabled hps) Quartus Pro 21.4 Any help would be useful!
Agilex7m i have configure 4GB ddr linux is not booting. I got architect time failure error.
Agilex7m I have configure 2GB DDR, linux is booting fine. But if I configure 4GB ddr linux is not booting. I got architect time failure error. But 2GB ddr configuration this error not came. I u-boot 4GB ddr is accessible but linux is not booting Boot logs init_mem_cal: Initial DDR calibration IO96B_0 succeed DDR: Calibration success is_mailbox_spec_compatible: IOSSM mailbox version: 1 DDR5: 4096 MiB ecc_interrupt_status: ECC error number detected on IO96B_0: 0 DDR5: size check success DDR5: firewall init success DDR5 init success QSPI: Reference clock at 500000 kHz Trying to boot from SPI Board ID is not in range 0 to 255 ## Checking hash(es) for config board-0 ... OK ## Checking hash(es) for Image atf ... crc32+ OK ## Checking hash(es) for Image uboot ... crc32+ OK ## Checking hash(es) for Image fdt-0 ... crc32+ OK NOTICE: BL31: v2.13.1(release):QPDS25.3.1_REL_GSRD_PR NOTICE: BL31: Built : 10:40:22, Nov 25 2025 U-Boot 2025.10-ga0db71cfad37-dirty (Dec 11 2025 - 10:49:42 +0000)socfpga_agilex7m CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53) Model: SoCFPGA Agilex7-M SoCDK DRAM: 2 GiB (total 4 GiB) Core: 38 devices, 22 uclasses, devicetree: separate NAND: 0 MiB MMC: mmc@ff808000: 0 Loading Environment from FAT... OK In: serial@ffc02000 Out: serial@ffc02000 Err: serial@ffc02000 Board ID is not in range 0 to 255 Net: eth0: ethernet@ff800000 Hit any key to stop autoboot: 0 SOCFPGA_AGILEX7M # SOCFPGA_AGILEX7M # SOCFPGA_AGILEX7M # SOCFPGA_AGILEX7M # bdinfo boot_params = 0x0000000000000100 DRAM bank = 0x0000000000000000 -> start = 0x0000000000000000 -> size = 0x0000000080000000 DRAM bank = 0x0000000000000001 -> start = 0x0000000100000000 -> size = 0x0000000080000000 flashstart = 0x0000000000000000 flashsize = 0x0000000000000000 flashoffset = 0x0000000000000000 baudrate = 115200 bps00 8N1 | NOR | Minicom 2.9 | VT102 | Offline | ttyACM0 relocaddr = 0x000000007fee9000 reloc off = 0x000000007fce9000 Build = 64-bit current eth = ethernet@ff800000 ethaddr = b6:97:a4:21:e2:4a IP addr = 169.254.65.121 fdt_blob = 0x000000007fae1950 lmb_dump_all: memory.count = 0x2 memory[0] [0x0-0x7fffffff], 0x80000000 bytes, flags: none memory[1] [0x100000000-0x17fffffff], 0x80000000 bytes, flags: none reserved.count = 0x3 reserved[0] [0x0-0x1ffffff], 0x2000000 bytes, flags: no-map reserved[1] [0x7eae1940-0x7fffffff], 0x151e6c0 bytes, flags: no-overwrite reserved[2] [0x17fff7000-0x17fffffff], 0x9000 bytes, flags: no-notify, no-overwrite devicetree = separate serial addr = 0x00000000ffc02000 width = 0x0000000000000004 shift = 0x0000000000000002 offset = 0x0000000000000000 clock = 0x0000000005f5e100 arch_number = 0x0000000000000000 TLB addr = 0x000000007ffe0000 irq_sp = 0x000000007fae1940 sp start = 0x000000007fae1940 Early malloc usage: 1608 / 2000 Failure log: init_mem_cal: Initial DDR calibration IO96B_0 succeed DDR: Calibration success is_mailbox_spec_compatible: IOSSM mailbox version: 1 DDR5: 4096 MiB ecc_interrupt_status: ECC error number detected on IO96B_0: 0 DDR5: size check success DDR5: firewall init success DDR5 init success QSPI: Reference clock at 500000 kHz Trying to boot from SPI Error: -22 Trying to boot from MMC1 Board ID is not in range 0 to 255 ## Checking hash(es) for config board-0 ... OK ## Checking hash(es) for Image atf ... crc32+ OK ## Checking hash(es) for Image uboot ... crc32+ OK ## Checking hash(es) for Image fdt-0 ... crc32+ OK NOTICE: BL31: v2.13.1(release):QPDS25.3.1_REL_GSRD_PR NOTICE: BL31: Built : 10:40:22, Nov 25 2025 U-Boot 2025.10 (Dec 11 2025 - 10:49:42 +0000)socfpga_agilex7m CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53) Model: SoCFPGA Agilex7-M SoCDK DRAM: 2 GiB (total 4 GiB) Core: 38 devices, 22 uclasses, devicetree: separate NAND: 0 MiB MMC: mmc@ff808000: 0 Loading Environment from FAT... OK In: serial@ffc02000 Out: serial@ffc02000 Err: serial@ffc02000 Board ID is not in range 0 to 255 Net: eth0: ethernet@ff800000 Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0(part 0) is current device Scanning mmc 0:1... Found U-Boot script /boot.scr.uimg 2411 bytes read in 3 ms (784.2 KiB/s) ## Executing script at 05ff0000 crc32+ Trying to boot Linux from device mmc0 Found kernel in mmc0 13661579 bytes read in 979 ms (13.3 MiB/s) ## Loading kernel (any) from FIT Image at 02000000 ... Using 'board-0' configuration Verifying Hash Integrity ... OK Trying 'kernel' kernel subimage Description: Linux Kernel Type: Kernel Image Compression: lzma compressed Data Start: 0x020000dc Data Size: 10439444 Bytes = 10 MiB Architecture: AArch64 OS: Linux Load Address: 0x06000000 Entry Point: 0x06000000 Hash algo: crc32 Hash value: 0ccd8e20 Verifying Hash Integrity ... crc32+ OK ## Loading fdt (any) from FIT Image at 02000000 ... Using 'board-0' configuration Verifying Hash Integrity ... OK Trying 'fdt-0' fdt subimage Description: socfpga_socdk_vanilla Type: Flat Device Tree Compression: uncompressed Data Start: 0x029f4cd4 Data Size: 32121 Bytes = 31.4 KiB Architecture: AArch64 Hash algo: crc32 Hash value: 262d6a47 Verifying Hash Integrity ... crc32+ OK Booting using the fdt blob at 0x29f4cd4 Working FDT set to 29f4cd4 Uncompressing Kernel Image to 6000000 Loading Device Tree to 000000007ead6000, end 000000007eae0d78 ... OK Working FDT set to 7ead6000 SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB Enabling QSPI at Linux DTB... Working FDT set to 7ead6000 libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND QSPI clock frequency updated RSU: Firmware or flash content not supporting RSU RSU: Firmware or flash content not supporting RSU RSU: Firmware or flash content not supporting RSU RSU: Firmware or flash content not supporting RSU Starting kernel ... Deasserting all peripheral resets [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Linux version 6.12.43-altera-gd16fc609d5a7 (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 14.3.0, GNU ld (GNU Binutils) 2.44.0.20250715) #1 SMP PREEMPT Tue Nov 25 16:06 :07 UTC 2025 [ 0.000000] KASLR disabled due to lack of seed [ 0.000000] Machine model: SoCFPGA Agilex7-M SoCDK [ 0.000000] efi: UEFI not found. [ 0.000000] earlycon: uart0 at MMIO32 0x00000000ffc02000 (options '115200n8') [ 0.000000] printk: legacy bootconsole [uart0] enabled [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000000000000, size 32 MiB [ 0.000000] OF: reserved mem: initialized node svcbuffer@0, compatible id shared-dma-pool [ 0.000000] OF: reserved mem: 0x0000000000000000..0x0000000001ffffff (32768 KiB) nomap non-reusable svcbuffer@0 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x000000017fffffff] [ 0.000000] NODE_DATA(0) allocated [mem 0x17f7fbe80-0x17f7fe4bf] [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000000000000-0x00000000ffffffff] [ 0.000000] DMA32 empty [ 0.000000] Normal [mem 0x0000000100000000-0x000000017fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000001ffffff] [ 0.000000] node 0: [mem 0x0000000002000000-0x000000007fffffff] [ 0.000000] node 0: [mem 0x0000000100000000-0x000000017fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000017fffffff] [ 0.000000] cma: Reserved 32 MiB at 0x000000007ca00000 on node -1 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.5 [ 0.000000] percpu: Embedded 25 pages/cpu s61784 r8192 d32424 u102400 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: ARM erratum 845719 [ 0.000000] alternatives: applying boot alternatives [ 0.000000] Kernel command line: earlycon panic=-1 root=/dev/mmcblk0p2 rw rootwait [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) [ 0.000000] Fallback order for Node 0: 0 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1048576 [ 0.000000] Policy zone: Normal [ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off [ 0.000000] software IO TLB: area num 4. [ 0.000000] software IO TLB: mapped [mem 0x0000000078a00000-0x000000007ca00000] (64MB) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 [ 0.000000] rcu: Preemptible hierarchical RCU implementation. [ 0.000000] rcu: RCU event tracing is enabled. [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=4. [ 0.000000] Trampoline variant of Tasks RCU enabled. [ 0.000000] Tracing variant of Tasks RCU enabled. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 [ 0.000000] RCU Tasks: Setting shift to 2 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=4. [ 0.000000] RCU Tasks Trace: Setting shift to 2 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=4. [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. [ 0.000000] timer_probe: no matching timers found [ 0.000000] Kernel panic - not syncing: Unable to initialise architected timer. [ 0.000000] CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 6.12.43-altera-gd16fc609d5a7 #1 [ 0.000000] Hardware name: SoCFPGA Agilex7-M SoCDK (DT) [ 0.000000] Call trace: [ 0.000000] dump_backtrace.part.0+0xd4/0xe0 [ 0.000000] show_stack+0x18/0x30 [ 0.000000] dump_stack_lvl+0x60/0x80 [ 0.000000] dump_stack+0x18/0x24 [ 0.000000] panic+0x168/0x360 [ 0.000000] time_init+0x30/0x50 [ 0.000000] start_kernel+0x544/0x6d0 [ 0.000000] __primary_switched+0x80/0x88
