Agilex 5 Premium Dev Kit Ethernet Performance
Hello! We built the golden sample image following the HPS GSRD User Guide with additional packages to profile/evaluate the board and experience performance problems when sending data over ethernet. The test setup is a host connected to the dev kit and sending data to test the throughput. First, we used iperf3 with zero copy flag, which caps at about 940 Mbit/s with almost no variation. Without zero copy, iperf3 caps at about ~880 Mbit/s with some variation down to 629 Mbit/s, see attachment 1.png. With our custom application that also does some additional work, we’d expect about 430-440 Mbit/s, but cap at about 300 Mbit/s, with lots of time spent in kernel again, see attachment 2.png. From the first investigation, we suspect the driver can’t keep up with the generated data and can’t send it fast enough to the host. We are wondering whether we can adjust something in the kernel (driver) or in the image so that we can improve the throughput with heavy workloads. Kind regards!47Views2likes0CommentsSupport Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA
Hi Altera Support Team, Greetings from Logic Fruit Technologies. This is Bhanu Pratap and I am working on the project in which we are using Agilex-7 SOC FPGA. Goal: Utilize Agiliex-HPS's capability on a Linux OS to control dynamic features of IP Cores at runtime. Problem Statement: We are facing an issue detecting SignalTap with SoC-based designs for runtime debugging while it's enabled and added from the Quartus project to generate the programming file. Brief Description: We are using Quartus 2025.1.1 and Altera's Agilex-7 Devkit(DKSIAAGI027FA: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit -> 4x F-Tile, Rev C). We downloaded the base GHRD design from Altera's GitHub webpage for the corresponding Quartus version. We are following each step to test GHRD and build generation for the Linux OS. We are using HPS First booting mode, we generated the build without modification and tested it. It's working fine according to the GSRD user guide. We have added a custom AXI4 Slave based CSR module to the HSP Lightweight bus to test basic register read/write using Platform Designer. We regenerated the build and re-tested but we are not getting the expected results so we added SignalTap for debugging. Build is generated using the STP file, programmed, and the OS is booting but it's not detecting SignalTap. This looks more like a process gap. We seek your support to fix this issue. Note: If we use an FPGA design without HPS, we are able to add and detect SignalTap. Seeking for urgent support. Thanks Bhanu Pratap31Views0likes1CommentS10 hps fpga2sdram bridge low speed
Hello, i have some problems I have a project with stratix 10 with hps I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width Via u-boot smc configured and enabled them, but measured speed is not enough. When I use onle one bridge my speed is approximately 32 gbit/s (bridge and master frequency 350 MHz) But when I use all 3 bridges it becomes 20 gbit/s I use avmm bridge to connect to axi fpga2sdram bridge with 128 bits width, max pending writes 16, max burst size 128, use only write to bridge ECC in emif (hmc) is disabled I tried to use QoS for bridges, set them to bypass P.S. If i use the same board with firmware without hps, i get 130 gbit/s (with disabled hps) Quartus Pro 21.4 Any help would be useful!84Views0likes5CommentsAgilex5 HPS running bare-metal code does not access FPGA fabric
I started with the following "Hello World" HPS OCRAM example: https://altera-fpga.github.io/rel-25.1/baremetal-embedded/agilex-5/e-series/premium/ug-baremetal-agx5e-premium/ I built the GHRD image with FPGA boot load set to "fabric first" and compiled the C code. With these changes, I am able to run the code and I can see the heartbeat LED toggle on the A5E premium development kit board. I am also able transmit data by writing the UART transmit register with my REG32 macro. However, I cannot access either H2F or LWH2F interfaces. I put Signal Tap on all arvalid/awvalid signals I and I do not see them toggle (I sanity checked the setup using the heartbeat counter). After looking at the documentation and the provided bare-metal drivers code, I cobbled together the following code to attempt to enable the HPS2 FPGA bridges: #define REG32(address) (*(volatile uint32_t*)address) #define REG64(address) (*(volatile uint64_t*)address) // Read the Reset manager registers uint32_t value32; value32 = REG32(0x10D1102C); printf("Reset manager initial value = 0x%08x \n", value32); // Drop the reset for SOC2FPGA bridges REG32(0x10D1102C) = 0; value32 = REG32(0x10D1102C); printf("Reset manager value after modification = 0x%08x \n", value32); printf("Enable FPGA bridges (NOTE: is this really an enable?)\n"); REG32(0x10D1205C) = 0x3; value32 = REG32(0x10D1205C); printf("Bridge enable register value after modification = 0x%08x \n", value32); Running this code I see: Reset manager initial value = 0x0000004f Reset manager value after modification = 0x00000000 Enable FPGA bridges Bridge enable register value after modification = 0x00000003 However, this loop does not show AWVALID come up on either AXI interface (I tried two different write macros to see if there is a difference): while (1) { printf("H2F: FPGA OCRAM write\n"); REG64(0x40000000) = 0x11223344; printf("H2LWF: LED controller write\n"); mem_quick_write_32(0x20010080, 0); } I feel like I am missing something obvious (like another enable) but I keep going over the code examples and the documentation and I can't find anything that could help. Any help is greatly appreciated.Solved263Views0likes16CommentsAgilex 5 with HPS
Hi, I have a question regarding Agilex 5 with HPS. I intend to deliver to the client a device based on Agilex 5 and HPS, but initially the HPS must remain fully offline. In other words, once the device is shipped, I need to ensure with 100% certainty that no software or program can be executed on the HPS, and that there is no possible way for the client to interact with or enable it prematurely. At the same time, I need to retain the ability to remotely deploy a new FPGA bitstream at a later stage, which will enable the HPS once the HPS software development is completed. Is such a workflow achievable on this platform?111Views0likes4CommentsAudio interface with Agilex 5 A5ED065BB32AI4S
Hello Team, I need your support on interfacing an audio device with the Agilex 5 SoC FPGA and not sure the which interface i have to use in Agilex 5. Kindly help me by sharing these details and references as well. Thank you, Regards, Jyothi.101Views0likes5CommentsUnique ID registers in Cyclone V
Hello everyone, I need to uniquely identify individual devices at runtime from the HPS (ARM Cortex-A9) side. Does the HPS side of the Cyclone V SoC have any built-in unique ID registers, such as: - A hardware serial number - A unique device ID - OTP (One-Time Programmable) fuses with unique identifiers - Any factory-programmed identification values What I've Tried: I've reviewed the Cyclone V documentation but haven't found clear information about unique ID registers accessible from the HPS side (unlike some other ARM SoCs that have dedicated UID registers). However I have seen Unique ID present in the FPGA side (https://www.intel.com/content/www/us/en/docs/programmable/683336/20-3/cores-user-guide.html), but this is not useful for my use case. Any guidance, documentation references, or code examples would be greatly appreciated! Thanks in advance!Solved148Views0likes4Comments25.3 PRO Release
Version: Release 25.3 PRO Quartus Build/TAG: B109/QPDS25.3_REL_GSRD_PR Release Date: October 10, 2025 Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7, Startix® 10, Arria® 10 Release Type: Major release/Binary release Binary Release Path: http://releases.rocketboards.org/2025.10/ Major Features Released Support of GHRD 2.0 in Agilex™ 5 which includes foundational boot to Linux, ability to create compatible phase 2 bitstreams, parameterized HPS for maximum performance and best practices. Support of GSRD 2.0 Yocto layers for the Agilex 5 E-Series Premium DevKit with OOBE daughtercard for the GHRD 2.0 baseline design. Agilex 5 GSRD Development User Experience Improvement through KAS using a graphical/text interface to configure a limited number of high-level options on top of simplified Yocto recipes. - GSRD 2.0 with Kas Build System Support for running Agilex 5 Simics Simulation under the GSRD 2.0 framework. Booting from SD Card and QSPI is supported. - Exercising Simics Simulation from GSRD 2.0 Support GHRD and GSRD for Agilex™ M-Series PRQ HBM2e for DK-Sl-AGM039EA development kit. The GSRD is capable of booting to Linux. - Build the GSRD for DK-DEV-AGM039EA Hypervisor Multi-OS Support Example, demonstrating Linux and Zephyr running side-by-side in the HPS cluster. - HPS Xen Hypervisor GSRD System Example Design: Agilex™ 3 FPGA and SoC C-Series Development Kit Support for monitoring of SEU errors from the SDM in the HPS in Agilex™ 7. Add capability to measure the latency of Linux SMC calls. Support Nios V Lockstep application with a fail-safe mechanism269Views3likes9CommentsAgilex 5 with HPS Cryptographic services and bootflow
Hi I have a question regarding boot flow on agilex 5 with HPS with security in mind. I am aware how this is typically implemented on other SoCs like NXP but as for the Agilex - I just started working on this SoC From what I understand (based on the docs and tf-a source code in particular VAB part) the flow is the following: SDM verfies fsbl signature and loads it SDM releses HPS from reset Fsbl loads next stages (BL31 BL33) each time communicating with SDM through mailbox asking SDM to verify the image signaturure Then we can be sure that we only use legitimate binaries. Am I right? I have found in the agilex 5 product table that some variants are equipped with Cryptographic services and some not. Are these Cryptographic services needed to perform the above flow? If the variant I have is not equipped with such IP is there any other way to securely boot all boot chain up to Linux?329Views0likes22CommentsAgilex 5 HPS porting guide
Hi, I'm wondering - what are the components that need to be adapted for a custom board based on Agilex 5. For the background e.g. on NXP Layerscape LS1028a in order to bring up a custom board we had to provide board-specific code in TF-A (DDR bring up for our memory config) and u-boot. I'm wondering what does it look like on Agilex5-based boards? I'm not talking about obvious things like device-tree but rather other parts like board-specific TF-A code and so on. Would be grateful to for some information that would allow me to estimate the necessary work. Also I'm talking about FPGA-first scenario if that matters.Solved131Views0likes2Comments