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HPark14's avatar
HPark14
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1 day ago

F2SDRAM fails to synthesize with custom logic

Hello guys, 

We are using Agilex5 SOC F2SDRAM bridge.

I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-level ports. Does anyone know why this is happening? Also, is there an example design for F2SDRAM available? The GHRD is not very helpful since it only includes the JTAG master.

I suspect it might be a design issue, so I even removed the adapter and connected it only within Qsys, but it’s still acting up like this.

Does anyone know why this is happening even though everything is clearly declared and connected?

Hudson

Arm Processor
Hps Arch

12 Replies

  • kbrunham_altera's avatar
    kbrunham_altera
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    1 day ago

    Hi Hudon,

    The error Quartus is reporting is illegal connectivity of the RDATA interface. The device legality requires that this interface be connected to registers. I suspect that in your axi_master_tester component you are leaving rdata unconnected or tied off to a constant. What is needed is to create preserved registers that you connect to this interface. 

    You can see a similar example in https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/custom_ip/h2f_termination_hw.tcl#L208

    • HPark14's avatar
      HPark14
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      11 hours ago

      "If more detailed messages were provided, I would debug it myself, but it only gives one-word answers like a parrot."

  • KelvinK_Altera's avatar
    KelvinK_Altera
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    15 hours ago

    Hi Hudson,

    To further debug, can you share the expended the error message regarding to the F2SDRAM error.

    • HPark14's avatar
      HPark14
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      11 hours ago

       

       

       

       

       

       

      Please refere to my message. So I made a register rdata but still synthesis fails.

       

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    13 hours ago

    Hi HPark14 

     

    This error behavior is expected because the F2SDRAM interface must be properly connected, as mentioned by my colleague, kbrunham_altera .
     

    For reference, you can refer to the public design example below. It connects the unused F2SDRAM port to a no_periph subsystem, which effectively terminates the interface and satisfies this design requirement:
    https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/tree/main/brd_altera_a5e065_premium_es/hw_base


    I hope this helps. 

     

     

     

    • HPark14's avatar
      HPark14
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      11 hours ago

      Thank you for your reply I am building the agilex5-demo designs. I will check the f2sdram reference design.

      Thanks~

    • HPark14's avatar
      HPark14
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      11 hours ago

      Example design is too difficult. If you patch it up with bridges and adapters, do you think users will like it? I'm uploading my user logic; I pasted it as is, but I keep getting RDATA errors. It's driving me crazy.

  • HPark14's avatar
    HPark14
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    10 hours ago

    "If more detailed messages were provided, I would debug it myself, but it only gives one-word answers like a parrot."

  • kbrunham_altera's avatar
    kbrunham_altera
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    6 hours ago

    Hi Hudson,

    I believe the issue is your rdata_r is not preserved and thus gets optimized away. You may be able to see that in the synthesis report.

    To preserve registers you can use the syn_preserve attribute on your declaration of the register.