Forum Discussion
Occasional ContributorF2SDRAM fails to synthesize with custom logic
Hello guys,
I've resolved this issue. Thank you for your support.
I created a r_out register and exported it to the top-level output
after that Quartus compilation succeeded.
Regular ContributorHi HPark14
This error behavior is expected because the F2SDRAM interface must be properly connected, as mentioned by my colleague, kbrunham_altera .
For reference, you can refer to the public design example below. It connects the unused F2SDRAM port to a no_periph subsystem, which effectively terminates the interface and satisfies this design requirement:
https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/tree/main/brd_altera_a5e065_premium_es/hw_base
I hope this helps.
HPark14Thank you for your reply I am building the agilex5-demo designs. I will check the f2sdram reference design.
Thanks~
Archer_AlteraHi HPark14,
I suggest you to add one AXI bridge component between f2sdram interface of HPS and AXI master interface of your own module. Then this error will disappear. You may see other error but they may be solved easier.
Hope this is helpful.
Archer_Altera
- HPark14
Example design is too difficult. If you patch it up with bridges and adapters, do you think users will like it? I'm uploading my user logic; I pasted it as is, but I keep getting RDATA errors. It's driving me crazy.
