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HPark14's avatar
HPark14
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1 day ago

F2SDRAM fails to synthesize with custom logic

Hello guys,  We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-lev...
Arm Processor
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KelvinK_Altera's avatar
KelvinK_Altera
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16 hours ago

Hi Hudson,

To further debug, can you share the expended the error message regarding to the F2SDRAM error.

  • HPark14's avatar
    HPark14
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    12 hours ago

     

     

     

     

     

     

    Please refere to my message. So I made a register rdata but still synthesis fails.

     

  • HPark14's avatar
    HPark14
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    12 hours ago

    Again I revised my test module

    It's very simple. but why quartus always says RDATA like a parrot?