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HPark14
Occasional Contributor
Occasional ContributorF2SDRAM fails to synthesize with custom logic
Hello guys, We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-lev...
kbrunham_altera
New Contributor
New ContributorHi Hudon,
The error Quartus is reporting is illegal connectivity of the RDATA interface. The device legality requires that this interface be connected to registers. I suspect that in your axi_master_tester component you are leaving rdata unconnected or tied off to a constant. What is needed is to create preserved registers that you connect to this interface.
You can see a similar example in https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/custom_ip/h2f_termination_hw.tcl#L208
HPark14Occasional Contributor
Occasional Contributor"If more detailed messages were provided, I would debug it myself, but it only gives one-word answers like a parrot."
