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HPark14's avatar
HPark14
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

F2SDRAM fails to synthesize with custom logic

Hello guys,  We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-lev...
Arm Processor
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kbrunham_altera's avatar
kbrunham_altera
Icon for New Contributor rankNew Contributor
1 month ago

Hi Hudson,

I believe the issue is your rdata_r is not preserved and thus gets optimized away. You may be able to see that in the synthesis report.

To preserve registers you can use the syn_preserve attribute on your declaration of the register.