New Contributor
Regular ContributorHi HPark14
This error behavior is expected because the F2SDRAM interface must be properly connected, as mentioned by my colleague, kbrunham_altera .
For reference, you can refer to the public design example below. It connects the unused F2SDRAM port to a no_periph subsystem, which effectively terminates the interface and satisfies this design requirement:
https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/tree/main/brd_altera_a5e065_premium_es/hw_base
I hope this helps.
New ContributorThank you for your reply I am building the agilex5-demo designs. I will check the f2sdram reference design.
Thanks~
