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HPark14
Occasional Contributor
Occasional ContributorF2SDRAM fails to synthesize with custom logic
Hello guys, We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-lev...
tehjingy_Altera
Regular Contributor
Regular ContributorHi HPark14
This error behavior is expected because the F2SDRAM interface must be properly connected, as mentioned by my colleague, kbrunham_altera .
For reference, you can refer to the public design example below. It connects the unused F2SDRAM port to a no_periph subsystem, which effectively terminates the interface and satisfies this design requirement:
https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/tree/main/brd_altera_a5e065_premium_es/hw_base
I hope this helps.
HPark14Occasional Contributor
Occasional ContributorExample design is too difficult. If you patch it up with bridges and adapters, do you think users will like it? I'm uploading my user logic; I pasted it as is, but I keep getting RDATA errors. It's driving me crazy.
