Forum Discussion
HPark14
Occasional Contributor
Occasional ContributorF2SDRAM fails to synthesize with custom logic
Hello guys, We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-lev...
HPark14Occasional Contributor
Occasional ContributorWhy does Quartus optimize?
RDATA is not connected.
tehjingy_AlteraRegular Contributor
Hi HPark14
I would suggest to take a look at the way the termination of f2sdram signal in the following file in the example:
f2sdram_terminator_reg_256_hw.tcl
f2sdram_terminator_64_hw.tcl
- tehjingy_Altera
Hi KoenVe
Unfortunately this is required. The expectation from the Quartus is to always have something connected to each F2SDRAM port (write and read).
