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HPark14's avatar
HPark14
Icon for Occasional Contributor rankOccasional Contributor
3 months ago
Solved

F2SDRAM fails to synthesize with custom logic

Hello guys,  We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-lev...
Arm Processor
Hps Arch
  • HPark14's avatar
    HPark14
    2 months ago

    Hello guys,

     I've resolved this issue. Thank you for your support.

    I created a r_out register and exported it to the top-level output 

    after that Quartus compilation succeeded.

HPark14's avatar
HPark14
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

Why does Quartus optimize?

RDATA is not connected.

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi HPark14 

     

    I would suggest to take a look at the way the termination of f2sdram signal in the following file in the example:

     

    f2sdram_terminator_reg_256_hw.tcl

    f2sdram_terminator_64_hw.tcl

     

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Hi KoenVe 

     

    Unfortunately this is required. The expectation from the Quartus is to always have something connected to each F2SDRAM port (write and read).