Need Step-by-Step Guide: Configuring Arria 10 HPS for UART0 Access (Tools & Workflow)

Hello Altera Community,

I am starting a new project using the Intel/Altera Arria 10 SoC FPGA. My immediate goal is to successfully configure the Hard Processor System (HPS) side of the chip and enable HPS UART0 access so I can view the boot messages and interact via a serial console terminal.

Since I am new to the Arria 10 HPS ecosystem, could someone provide a detailed, step-by-step workflow of the procedure? Specifically, I would appreciate guidance on:

1. Required Tools: Which exact software versions (Quartus Prime Pro, SoC EDS, Arm DS, etc.) are recommended for a stable Arria 10 HPS development pipeline?

2. Platform Designer (Qsys) Setup: What are the specific steps to route and configure UART0 pins, clocks, and DDR parameters inside Platform Designer?

3. Bootloader Generation: How do I correctly handle the hardware handoff files to generate the U-Boot/SPL bootloader using the SoC EDS utilities?

4. Target OS: I intend to use Bare-Metal . What are the final steps to write these images to a boot medium (like an SD card / QSPI flash) to verify that UART0 is transmitting successfully?

If there are any updated Golden System Reference Designs (GSRD), specific user guides, or community tutorials that outline this exact UART0 baseline setup, please share the links.

Thank you in advance for your time and guidance!

Best regards,

Team D&D
ESSEN