Title: Request for From-Scratch Guide: Configuring Arria 10 HPS IP and EMIF for Bare-Metal UART0 Development
Hello Altera Support Team,
I am starting a new project using the Intel/Altera Arria 10 SoC FPGA. My immediate goal is to successfully configure the Hard Processor System (HPS) side of the chip from scratch to enable HPS UART0 access for a pure Bare-Metal C application (No Linux/OS).
Could you please provide clarity on the following specific requirements?
Hardware Configuration & IP Requirements (From Scratch)
- IP Blocks: Is configuring the Arria 10 Hard Processor System IP block alone sufficient to access HPS UART0, or must I instantiate and connect additional IP blocks (such as the Arria 10 External Memory Interface / EMIF) in Platform Designer?
- Platform Designer Connectivity: If the EMIF IP is mandatory for a bare-metal boot/initialization baseline, what are the precise connection rules between the HPS memory controller ports and the EMIF Avalon interfaces?
Software Design Workflow & Toolchain Pipeline
- Post-Compilation Step: Once the Quartus Prime Pro project compiles successfully and generates the hardware handoff files, what is the exact step-by-step procedure to transition to software development?
- IDE & Compiler Selection: Which specific modern software tools (e.g., Arm Development Studio Intel SoC FPGA Edition, SoC EDS command shell utilities) should be used to compile and debug a bare-metal application?
- C-Code Workspace Setup: Where and how do we write the main C application? Does Altera provide standard SoC FPGA Hardware Library (HWLIB) drivers or a clean template project specifically for Arria 10 bare-metal peripherals?
Execution & Verification Workflow
- JTAG Debugging vs Bootloader: For an initial scratchpad environment, can we bypass U-Boot/SPL entirely and execute code directly via JTAG scripts in Arm DS?
If there are any current application notes, standalone bare-metal project examples, or targeted user guides addressing this exact "Hello World" serial baseline for Arria 10, please share the links.
Thank you for your time, support, and technical guidance.
Best regards,
Team D&D
ESSEN
New Contributor
