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Essen's avatar
Essen
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1 month ago

Need Step-by-Step Guide: Configuring Arria 10 HPS for UART0 Access (Tools & Workflow)

Hello Altera Community, I am starting a new project using the Intel/Altera Arria 10 SoC FPGA. My immediate goal is to successfully configure the Hard Processor System (HPS) side of the chip and enab...
Hps Arch
Hps Boot
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Qingrui_H_Intel's avatar
Qingrui_H_Intel
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1 month ago

Hi,

We do not have an available Arria10 Baremetal example design or demo now. But we had a HWLIB based example design for your reference.

https://www.rocketboards.org/foswiki/Documentation/HWLib

Besides this, some comments for your questions may help you create your design.

Hardware Configuration & IP Requirements (From Scratch)

  • IP Blocks: Is configuring the Arria 10 Hard Processor System IP block alone sufficient to access HPS UART0, or must I instantiate and connect additional IP blocks (such as the Arria 10 External Memory Interface / EMIF) in Platform Designer?

          >>> In theory, HPS IP is sufficient to access HPS UART0, but all the current designs are based on HPS + HPS EMIF design. So it's highly suggested to use HPS + HPS EMIF as a start.

  • Platform Designer Connectivity: If the EMIF IP is mandatory for a bare-metal boot/initialization baseline, what are the precise connection rules between the HPS memory controller ports and the EMIF Avalon interfaces?

         >>> You just need to connect HPS and HPS EMIF by clicking the dots in connection parts in platform designer , just like what GHRD did. If you have no experience about how to create a design in  platform designer. Here is an useful document, and GHRD is also a good reference.

https://docs.altera.com/r/docs/683609/26.1/quartus-prime-pro-edition-user-guide-platform-designer/answers-to-top-faqs

 

Software Design Workflow & Toolchain Pipeline

  • Post-Compilation Step: Once the Quartus Prime Pro project compiles successfully and generates the hardware handoff files, what is the exact step-by-step procedure to transition to software development?

>>>  The qts-filter-a10.sh can be used to use the handoff files to generate u-boot-spl and u-boot-spl.dtb.bin file. You can get the details in the HWLIB example design

  • IDE & Compiler Selection: Which specific modern software tools (e.g., Arm Development Studio Intel SoC FPGA Edition, SoC EDS command shell utilities) should be used to compile and debug a bare-metal application?

>>> HWLIB, ARM DS and Quartus are needed. The installation are also listed in the example design.

  • C-Code Workspace Setup: Where and how do we write the main C application? Does Altera provide standard SoC FPGA Hardware Library (HWLIB) drivers or a clean template project specifically for Arria 10 bare-metal peripherals?

>>> HWLIB is provided.

Execution & Verification Workflow

  • JTAG Debugging vs Bootloader: For an initial scratchpad environment, can we bypass U-Boot/SPL entirely and execute code directly via JTAG scripts in Arm DS? 

>>> Yes, you can use ARM DS for debugging. But it's highly suggested to use SPL for initialization. 

Essen's avatar
Essen
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1 month ago

Title: Toolchain & Hardware Clarification: Arria 10 HPS Bare-Metal Workflow Using SoC EDS 20.1 and Linaro on Windows (No Arm DS)

Hello Altera Support Team,

I am developing a new project from scratch on an Intel/Altera Arria 10 SoC FPGA. My target goal is to configure the Hard Processor System (HPS) side of the chip to enable HPS UART0 access for a pure Bare-Metal C application (No Linux/OS).

I am seeking technical guidance regarding our current hardware compilation errors and a definitive confirmation on whether our available software toolchain is sufficient to completely build, generate a boot image, and load the files onto the target hardware.

Software Toolchain, Boot Image Generation & Board Loading Constraints

We are developing entirely on a Windows environment (not Linux). Due to licensing limitations, we do not have Arm Development Studio (Arm DS) installed, nor do we have an active license for it.

Our current local software setup consists exclusively of:

Intel SoC EDS Command Shell (Version 20.1)

Linaro Bare-Metal Toolchain (arm-eabi- / arm-none-eabi- GCC)

Our Specific Questions:

Is it compulsory to use Arm DS for Arria 10 bare-metal development, or are SoC EDS 20.1 and the Linaro bare metal toolchain enough to write C code, compile it, create a bootable image, and load/program that file into the physical board from a Windows command line?

If this combination is sufficient, what is the exact command-line workflow to build the application and package it into a final boot image?

Without Arm DS, how can we download and run our compiled bare-metal binary or boot image directly into the HPS on-chip RAM/DDR using standard free tools like the Quartus Programmer, Intel System Console, or command-line JTAG tools over a USB-Blaster II?

Please provide any relevant standalone bare-metal reference designs, programming scripts, or user guides that match this Windows command-line loading ecosystem for the Arria 10.

Thank you for your time and guidance.

Best regards,

Team D&D
ESSEN