Support Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA
Hi Altera Support Team, Greetings from Logic Fruit Technologies. This is Bhanu Pratap and I am working on the project in which we are using Agilex-7 SOC FPGA. Goal: Utilize Agiliex-HPS's capability on a Linux OS to control dynamic features of IP Cores at runtime. Problem Statement: We are facing an issue detecting SignalTap with SoC-based designs for runtime debugging while it's enabled and added from the Quartus project to generate the programming file. Brief Description: We are using Quartus 2025.1.1 and Altera's Agilex-7 Devkit(DKSIAAGI027FA: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit -> 4x F-Tile, Rev C). We downloaded the base GHRD design from Altera's GitHub webpage for the corresponding Quartus version. We are following each step to test GHRD and build generation for the Linux OS. We are using HPS First booting mode, we generated the build without modification and tested it. It's working fine according to the GSRD user guide. We have added a custom AXI4 Slave based CSR module to the HSP Lightweight bus to test basic register read/write using Platform Designer. We regenerated the build and re-tested but we are not getting the expected results so we added SignalTap for debugging. Build is generated using the STP file, programmed, and the OS is booting but it's not detecting SignalTap. This looks more like a process gap. We seek your support to fix this issue. Note: If we use an FPGA design without HPS, we are able to add and detect SignalTap. Seeking for urgent support. Thanks Bhanu Pratap
Release 25.3.1 PRO
Version: Release 25.3.1 PRO Quartus Build/TAG: B100/QPDS25.3.1_REL_GSRD_PR Release Date: January 16, 2026 Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7 Release Type: Major release/Binary release Binary Release Path: http://releases.rocketboards.org/2026.01/ Release Page: https://github.com/altera-fpga/gsrd-socfpga/releases/tag/QPDS25.3.1_REL_GSRD_PR Major Features Released Roll-your-own Linux GSRD 2.0 for Agilex™ 5 PDK OOBE DC on baseline design. Created the GSRD 2.0 rol-your-own Linux script for the Agilex™ 5 E-Series Premium DevKit with OOBE daughtercard for the GHRD 2.0 baseline design. Removed Legacy GSRD from Agilex™ 5 Premium Development kit + OOB Daughter card, keeping only Baseline (GSRD 2.0).
S10 hps fpga2sdram bridge low speed
Hello, i have some problems I have a project with stratix 10 with hps I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width Via u-boot smc configured and enabled them, but measured speed is not enough. When I use onle one bridge my speed is approximately 32 gbit/s (bridge and master frequency 350 MHz) But when I use all 3 bridges it becomes 20 gbit/s I use avmm bridge to connect to axi fpga2sdram bridge with 128 bits width, max pending writes 16, max burst size 128, use only write to bridge ECC in emif (hmc) is disabled I tried to use QoS for bridges, set them to bypass P.S. If i use the same board with firmware without hps, i get 130 gbit/s (with disabled hps) Quartus Pro 21.4 Any help would be useful!
Agilex 5/3 FreeRTOS SMP Support
Stable Version: v25.4 Quartus Version: 25.4 Supported devices: Agilex™ 3 and Agilex™ 5 Source : https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v25.4-SMP Release Date: March 30, 2026 Hello Everyone, FreeRTOS port for A55/A76 HPS now supports SMP. visit the GitHub page for instructions on how to get started. Features and comments Features Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP (A55 x 2 or A76 x 2) Supported features Limitations/ Known issues A55 boot Yes Yes Yes Yes Single core boot, Dual core SMP A76 boot NA Yes NA Yes Single core boot, Dual core SMP QSPI boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes NAND boot No No No No Clk mngr driver Yes Yes Yes Yes API to get clock speed of different blocks Reset mngr driver Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory to memory transfer Only support memory to memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User defined and free running modes UART driver Yes Yes Yes Yes Full duplex Tx and Rx DMA not supported (Planned for future release I2C driver Yes Yes Yes Yes Master mode write and read Standard and fast modes DMA not supported (Planned for future release I3C driver Yes Yes Yes Yes Master mode write and read i3c and legacy i2c devices IBI not supported (Planned for future release) SPI driver Yes Yes Yes Yes Master mode write and read DMA is not supported QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase NAND driver No No No No SDM mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU enable support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes standard and HS speeds SDMMC and eMMC devices Fat FS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP and DHCP IPv4 and IPv6 support USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT diver Yes Yes Yes Yes interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver NT Yes NT Yes Enable, Disable Reboot mngr Yes Yes Yes Yes Warm/Cold reboot FPGA manager Yes Yes Yes Yes FPGA configuration Yes: Feature available and tested, No: Feature not available in SDK, NA : Not applicable , NT: Not tested Note: If you find any issues, please raise an issue in the GitHub page. For more support/assistance visit our website .
Cyclone5 SoC: U-Boot not detecting USB-HUB
Hello there, I'm working on a design on top of a Chameleon96 Board (CycloneV based), featuring a USB OTG Chip USB3300, and connected to it an USB 2513B Hub. My issue is that neither U-Boot or Linux are able to detect the USB Hub connected to the USB3300. This used to work with older U-Boot versions and are still working on my board, but I was not able to reproduce such behavior with up-to-date versions (cloned from https://github.com/altera-fpga/u-boot-socfpga and https://github.com/altera-fpga/linux-socfpga). The Chameleon96 has two GPIO pins to control the reset of the mentioned USB chips, with a fixed configuration on the USB 2513B (the I2C interface is not exposed). With my version (U-Boot 2025.07-gd4f268660a70-dirty and Linux 6.12.33-g3234b1ed8956), the USB OTG is detected and the hub registered with logs like the following: [ 0.883275] dwc2 ffb40000.usb: supply vusb_d not found, using dummy regulator [ 0.890619] dwc2 ffb40000.usb: supply vusb_a not found, using dummy regulator [ 0.898034] dwc2 ffb40000.usb: Configuration mismatch. dr_mode forced to host [ 0.905721] dwc2 ffb40000.usb: DWC OTG Controller [ 0.910454] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1 [ 0.917571] dwc2 ffb40000.usb: irq 32, io mem 0xffb40000 [ 0.923324] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, b2 [ 0.931588] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber1 [ 0.938800] usb usb1: Product: DWC OTG Controller [ 0.943509] usb usb1: Manufacturer: Linux 6.12.33-g3234b1ed8956 dwc2_hsotg [ 0.950362] usb usb1: SerialNumber: ffb40000.usb [ 0.955682] hub 1-0:1.0: USB hub found [ 0.959499] hub 1-0:1.0: 1 port detected but the connected USB hub never shows up. Similarly 'usb start' from the U-Boot prompt just shows something called U-Boot Root Hub: => usb start starting USB... USB DWC2 Bus usb@ffb40000: 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub Older u-boot versions (and linux) are able to detect the USB hub after 'usb start'. In this case, the root hub is named DWT OTC RootHub, and I don't know if this is just a change of naming somewhere or something wrong is also happening while detecting the USB3300 Hub: SOCFPGA_CHAMELEON96 # usb start (Re)start USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found SOCFPGA_CHAMELEON96 # usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | DWC OTG RootHub | +-2 Hub (480 Mb/s, 2mA) the linux kernel (4.1.33-ltsi-altera) is also able to detect the USB Hub as can be seen in these logs: [ 0.913203] ffb40000.usb supply vusb_d not found, using dummy regulator [ 0.919864] ffb40000.usb supply vusb_a not found, using dummy regulator [ 0.957196] dwc2 ffb40000.usb: EPs: 16, dedicated fifos, 8064 entries in SPRM [ 1.817295] dwc2 ffb40000.usb: DWC OTG Controller [ 1.822011] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1 [ 1.829076] dwc2 ffb40000.usb: irq 44, io mem 0x00000000 [ 1.834617] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 [ 1.841394] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber1 [ 1.848596] usb usb1: Product: DWC OTG Controller [ 1.853282] usb usb1: Manufacturer: Linux 4.1.33-ltsi-altera-svn260 dwc2_hsog [ 1.860481] usb usb1: SerialNumber: ffb40000.usb [ 1.865670] hub 1-0:1.0: USB hub found [ 1.869457] hub 1-0:1.0: 1 port detected ... [ 2.367190] usb 1-1: new high-speed USB device number 2 using dwc2 [ 2.577385] usb 1-1: New USB device found, idVendor=0424, idProduct=2513 [ 2.584069] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.591939] hub 1-1:1.0: USB hub found [ 2.595782] hub 1-1:1.0: 3 ports detected I think I've ported all the needed configuration to the u-boot sources (basically resetting the USB hub using the attached GPIOs, and I also tried the reset sequence manually from U-Boot with the gpio command) and I'm not able to figure out how to find where the issue might be. I've forked u-boot sources here: https://github.com/teiram/u-boot-socfpga/, using the socfpga_chameleon96_defconfig configuration. Could you please support me in order to troubleshoot what the issue might be? I tried to backport my changes to some different branches on u-boot-socpfga but got the same results or even worse (no boot at all). I also have sources for a working U-Boot but they are quite old and the configuration changed sensibly since. I think all the needed options are set. Cheers, Manuel
Agilex 5 HPS EMAC2 SWR bit in DMA_Mode Register Not Clearing
Hello, Following section 5.1.7 of the Agilex 5 Hard Processor System Technical Reference Manual, and based on what I found in U-Boot and Linux, I am writing an Ethernet driver that uses EMAC2 with an RGMII interface. I am currently stuck at the software reset using the SWR bit of the DMA_Mode register, as it remains set to 1. Our boot flow on the AXE5-Eagle board is ATF -> U-Boot -> our OS. We use the U-Boot from https://github.com/ArrowElectronics/u-boot-socfpga/tree/socfpga_v2025.07 with some adaptations to load our OS instead of Linux. When I read the DMA_Mode register before performing any EMAC setup in our OS, I already see the value set to 1. After bringing the PHY out of reset and setting the SWR bit again, it does not clear. I also tried putting the EMAC into reset using the per0modrst register, setting the System Manager tsn2 register to 1 again, and then bringing the EMAC out of reset. This did not help, and after resetting the EMAC I can no longer read PHY registers over MDIO. When I load Linux instead of our OS, I can see that the reset using the SWR bit works correctly, but I can’t find what is missing in my implementation. Any help would be greatly appreciated. Thanks, Sarah For additional context, I read the following values before putting the EMAC2 in reset: PHY ID1: 0x283 Main PLLGLOB: 35000103 Per PLLGLOB: 35000103 DMA_Mode: 00000001 SYSMGR_TSN2: 1 EMAC2_DWCXG_CORE_MAC_TX_CONF: 0 CLKMGR_PERPLL_EN: fffffff CLKMGR_PERPLL_BYPASS: 0 CLKMGR_PERPLL_EMACCTL: 0 CLKMGR_CTLGRP_EMACACTR: 10001 CLKMGR_CTLGRP_EMACPTPCTR: 0 CLKMGR_CTLGRP_EXTCNTRST: 0
Agilex 5 HPS EMAC2 SWR bit in DMA_Mode Register Not Clearing
Hello, Following section 5.1.7 of the Agilex 5 Hard Processor System Technical Reference Manual, and based on what I found in U-Boot and Linux, I am writing an Ethernet driver that uses EMAC2 with an RGMII interface. I am currently stuck at the software reset using the SWR bit of the DMA_Mode register, as it remains set to 1. Our boot flow on the AXE5-Eagle board is ATF -> U-Boot -> our OS. We use the U-Boot from https://github.com/ArrowElectronics/u-boot-socfpga/tree/socfpga_v2025.07 with some adaptations to load our OS instead of Linux. When I read the DMA_Mode register before performing any EMAC setup in our OS, I already see the value set to 1. After bringing the PHY out of reset and setting the SWR bit again, it does not clear. I also tried putting the EMAC into reset using the per0modrst register, setting the System Manager tsn2 register to 1 again, and then bringing the EMAC out of reset. This did not help, and after doing this I can no longer read PHY registers over MDIO. When I load Linux instead of our OS, I can see that the reset using the SWR bit works correctly, but I can’t find what is missing in my implementation. Any help would be greatly appreciated. Thanks, Sarah For additional context, I read the following values before putting the EMAC2 in reset: PHY ID1: 0x283 Main PLLGLOB: 35000103 Per PLLGLOB: 35000103 DMA_Mode: 00000001 SYSMGR_TSN2: 1 EMAC2_DWCXG_CORE_MAC_TX_CONF: 0 CLKMGR_PERPLL_EN: fffffff CLKMGR_PERPLL_BYPASS: 0 CLKMGR_PERPLL_EMACCTL: 0 CLKMGR_CTLGRP_EMACACTR: 10001 CLKMGR_CTLGRP_EMACPTPCTR: 0 CLKMGR_CTLGRP_EXTCNTRST: 0Agilex 5 HPS TEE
Hi, Is Arm Trust Zone supported on HPS? If so is the implementation of TEE supported on Agilex 5? I've checked TF-A sources and it seems that BL2 on this platform loads only BL31 and BL33. How about BL32? Is there an OP-TEE support? If not, are there any plans to provide it in the nearest feature?
