Agilex 5 HPS EMAC2 SWR bit in DMA_Mode Register Not Clearing

Hello,

Following section 5.1.7 of the Agilex 5 Hard Processor System Technical Reference Manual, and based on what I found in U-Boot and Linux, I am writing an Ethernet driver that uses EMAC2 with an RGMII interface. I am currently stuck at the software reset using the SWR bit of the DMA_Mode register, as it remains set to 1.

Our boot flow on the AXE5-Eagle board is ATF -> U-Boot -> our OS. We use the U-Boot from https://github.com/ArrowElectronics/u-boot-socfpga/tree/socfpga_v2025.07 with some adaptations to load our OS instead of Linux.

When I read the DMA_Mode register before performing any EMAC setup in our OS, I already see the value set to 1. After bringing the PHY out of reset and setting the SWR bit again, it does not clear.

I also tried putting the EMAC into reset using the per0modrst register, setting the System Manager tsn2 register to 1 again, and then bringing the EMAC out of reset. This did not help, and after doing this I can no longer read PHY registers over MDIO.

When I load Linux instead of our OS, I can see that the reset using the SWR bit works correctly, but I can’t find what is missing in my implementation.

Any help would be greatly appreciated.

Thanks,

Sarah

For additional context, I read the following values before putting the EMAC2 in reset:

PHY ID1: 0x283

Main PLLGLOB: 35000103

Per PLLGLOB: 35000103

DMA_Mode: 00000001

SYSMGR_TSN2: 1

EMAC2_DWCXG_CORE_MAC_TX_CONF: 0

CLKMGR_PERPLL_EN: fffffff

CLKMGR_PERPLL_BYPASS: 0

CLKMGR_PERPLL_EMACCTL: 0

CLKMGR_CTLGRP_EMACACTR: 10001

CLKMGR_CTLGRP_EMACPTPCTR: 0

CLKMGR_CTLGRP_EXTCNTRST: 0