A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected.

Hello monkstein88,

The issue was happened on the following code.

https://github.com/altera-fpga/u-boot-socfpga/blob/socfpga_v2026.01/drivers/fpga/socfpga_gen5.c#L158

static int fpgamgr_program_poll_initphase(void)
{
    unsigned long i;

    /* Additional clocks for the CB to enter initialization phase */
    if (fpgamgr_dclkcnt_set(0x4))
        return -5;

    /* (4) wait until FPGA enter init phase or user mode */
    for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
        if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
            break;
        if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
            break;
    }

    /* If not in configuration state, return error */
    if (i == FPGA_TIMEOUT_CNT)
        return -6;

    return 0;
}

This issue most likely is happened on the mismatch of MSEL and generated RBF, or Device OPN mismatch.

1) Check SOF. Please configure your SOF by Quartus Programmer via JTAG.

If it fails, Device OPN is incorrect. Please update DEVICE section in your qmtech_c5soc_kfb_dual_sdram_ghrd.qsf.

2) Check the compression mode of the RBF. Here are details of the settings.

3) Check your power supply. Does the output current of your power supply meet requirement of the board?

Best regards,

 Yoshiaki Saito

Hello monkstein88,

Thank you for the update.

I'm glad to hear .rbf without compression works fine.

Could you please try the following combination?

Table 27.  Configuration Schemes for FPGA Configuration by the HPS

https://docs.altera.com/r/docs/683126/21.2/cyclone-v-hard-processor-system-technical-reference-manual/fpga-configuration?tocId=oT8kgUpEZokq8aJ3ItYu8g

Best regards,

 Yoshiaki Saito

Ok, I will try to lay out the original problem I have been encountering.

Currently I am experiencing a persistent issue with a QMTech Cyclone V SoC board (a very close clone of the Terasic DE10-Nano Board), trying to load the fpga configuration (.rbf) while the board is booting (U-Boot). While the .rbf is being loaded, I get an error: 'Command 'load' failed: Error -6' . 

Overall, the whole booting process works, my system is able to  go through the whole process: UBoot SPL -> UBoot -> Linux (logjn prompt). But a phase in between - which is the FPGA configuration loading is failing.  

Here's the U-Boot shell excerpt, where I prompt the system for a couple of things and then try to fpga load the .rbf file:

=> fpga info
Altera Device
Descriptor @ 0x3ffec7a0
Family:         SoC FPGA
Interface type: Fast Passive Parallel (FPP)
Device Size:    4294967295 bytes
Cookie:         0x0 (0)
No Device Function Table.
=>
=> printenv
arch=arm
baudrate=115200
board=c5soc-kfb-dual-sdram
board_name=c5soc-kfb-dual-sdram
boot_a_script=load ${devtype} ${devnum}:${distro_bootpart} ${scriptaddr} ${prefix}${script}; source ${scriptaddr}
boot_efi_binary=load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} efi/boot/bootarm.efi; if fdt addr -q ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r};else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi
boot_efi_bootmgr=if fdt addr -q ${fdt_addr_r}; then bootefi bootmgr ${fdt_addr_r};else bootefi bootmgr;fi
boot_extlinux=sysboot ${devtype} ${devnum}:${distro_bootpart} any ${scriptaddr} ${prefix}${boot_syslinux_conf}
boot_net_usb_start=usb start
boot_prefixes=/ /boot/
boot_script_dhcp=boot.scr.uimg
boot_scripts=boot.scr.uimg boot.scr
boot_syslinux_conf=extlinux/extlinux.conf
boot_targets=mmc0 qspi pxe dhcp
bootcmd=load mmc 0:1 ${loadaddr} soc_system.rbf && fpga load 0 ${loadaddr} $filesize; sysboot mmc 0:1 any ${scriptaddr} /extlinux/extlinux.conf
bootcmd_dhcp=devtype=dhcp; run boot_net_usb_start; if dhcp ${scriptaddr} ${boot_script_dhcp}; then source ${scriptaddr}; fi;setenv efi_fdtfile ${fdtfile}; if test -z "${fdtfile}" -a -n "${soc}"; then setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; fi; setenv efi_old_vci ${bootp_vci};setenv efi_old_arch ${bootp_arch};setenv bootp_vci PXEClient:Arch:00010:UNDI:003000;setenv bootp_arch 0xa;if dhcp ${kernel_addr_r}; then tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};if fdt addr -q ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r}; else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi;fi;setenv bootp_vci ${efi_old_vci};setenv bootp_arch ${efi_old_arch};setenv efi_fdtfile;setenv efi_old_arch;setenv efi_old_vci;
bootcmd_mmc0=devnum=0; run mmc_boot
bootcmd_pxe=run boot_net_usb_start; dhcp; if pxe get; then pxe boot; fi
bootcmd_qspi=run qspiload; run qspiboot
bootdelay=2
bootm_size=0xa000000
bootmode=sd
cpu=armv7
distro_bootcmd=for target in ${boot_targets}; do run bootcmd_${target}; done
efi_dtb_prefixes=/ /dtb/ /dtb/current/
fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};then source ${scriptaddr}; fi
fdt_addr_r=0x02000000
fdtcontroladdr=3bf74610
fdtfile=socfpga_cyclone5_kfb_dual_sdram.dtb
fpgatype=cv_se_a6
kernel_addr_r=0x01000000
load_efi_dtb=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${prefix}${efi_fdtfile}
loadaddr=0x01000000
mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi
mtdids=nor0=ff705000.spi.0
prog_core=if load mmc 0:1 ${loadaddr} fit_spl_fpga.itb;then fpga loadmk 0 ${loadaddr}:fpga-core-1; fi
pxefile_addr_r=0x02200000
ramdisk_addr_r=0x02300000
scan_dev_for_boot=echo Scanning ${devtype} ${devnum}:${distro_bootpart}...; for prefix in ${boot_prefixes}; do run scan_dev_for_extlinux; run scan_dev_for_scripts; done;run scan_dev_for_efi;
scan_dev_for_boot_part=part list ${devtype} ${devnum} -bootable devplist; env exists devplist || setenv devplist 1; for distro_bootpart in ${devplist}; do if fstype ${devtype} ${devnum}:${distro_bootpart} bootfstype; then part uuid ${devtype} ${devnum}:${distro_bootpart} distro_bootpart_uuid ; run scan_dev_for_boot; fi; done; setenv devplist
scan_dev_for_efi=setenv efi_fdtfile ${fdtfile}; if test -z "${fdtfile}" -a -n "${soc}"; then setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; fi; for prefix in ${efi_dtb_prefixes}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${efi_fdtfile}; then run load_efi_dtb; fi;done;run boot_efi_bootmgr;if test -e ${devtype} ${devnum}:${distro_bootpart} efi/boot/bootarm.efi; then echo Found EFI removable media binary efi/boot/bootarm.efi; run boot_efi_binary; echo EFI LOAD FAILED: continuing...; fi; setenv efi_fdtfile
scan_dev_for_extlinux=if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${boot_syslinux_conf}; then echo Found ${prefix}${boot_syslinux_conf}; run boot_extlinux; echo EXTLINUX FAILED: continuing...; fi
scan_dev_for_scripts=for script in ${boot_scripts}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${script}; then echo Found U-Boot script ${prefix}${script}; run boot_a_script; echo SCRIPT FAILED: continuing...; fi; done
scriptaddr=0x02100000
scriptfile=u-boot.scr
soc=socfpga
socfpga_legacy_reset_compat=1
stderr=serial
stdin=serial
stdout=serial
usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi
vendor=qmtech
ver=U-Boot 2024.07-36780-g67806ba5853-dirty (May 09 2026 - 16:08:17 +0300)

Environment size: 4441/8188 bytes

=>
=>

=> fatls mmc 0:1
  6275664   zImage
            extlinux/
  2082772   soc_system.rbf
    25844   socfpga_cyclone5_kfb_dual_sdram.dtb

3 file(s), 1 dir(s)

=> load mmc 0:1 ${loadaddr} soc_system.rbf;
2082772 bytes read in 111 ms (17.9 MiB/s)
=> fpga load 0 ${loadaddr} $filesize;
Command 'load' failed: Error -6
=>

=>

 I've attached  a zip which contains a full boot log, defconfig and .config file produced after building U-Boot. Also pics of what my Quartus projects settings are - regarding the generated and used .rbf file. 

FYI, I've tried several MSEL Dip Sw settings : "00000" and "01010" but nothing works.

Please advise :?

-Monk

Hello monkstein88,

We apologize for the inconvenience.

I will check the original topic.

Best regards,

Yoshiaki Saito

Greetings Yoshiaki,

So, first, I actually tried something first yesterday after writing my original message and I have good results. In the Quartus project settings - I disabled the compression for the bitstream and also  set the Configuration scheme to Passive Parallel x16.

Also, in the same project settings, I enabled the generation of the Raw Binary File (.rbf).

So, now when the Quartus project  is rebuild (as normal) it will also create the .rbf file I need for U-boot. Then I recompiled the project, and just used to .sof file to program directly the FPGA part of the device: 

And it was all successful. Actually, the FPGA portion of the design contains a Qsys, that features several different JTAG masters and JTAG Uart. And after the design (.sof) was programmed -  those became visible when polling the jtagconfig with the USB-Blaster still attached:

Thus, the configuration files (.sof) and (.rbf) - match and work with the SoC FPGA on the board correctly. Note: At this point the produced .sof and .rbf files are 'uncompressed' and configured for 'FPP x16'.

Then, I took the .rbf file (from the prev post) and put in (overwriting the older .rbf file) to the FAT partion of the SD Card, and set the MSEL [4:0] = '00000' (All are  'ON' )   , and powered up the board. And this time there were no errors when loading the .rbf.

U-Boot SPL 2024.07-36780-g67806ba5853-dirty (May 09 2026 - 16:08:17 +0300)
Trying to boot from MMC1


U-Boot 2024.07-36780-g67806ba5853-dirty (May 09 2026 - 16:08:17 +0300)

CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT:  SD/MMC Internal Transceiver (3.0V)
DRAM:  1 GiB
Core:  29 devices, 15 uclasses, devicetree: separate
MMC:   dwmmc0@ff704000: 0
Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: QMTECH C5SOC KFB Dual SDRAM
Net:
Error: ethernet@ff702000 No valid MAC address found.
No ethernet found.

Hit any key to stop autoboot:  0
=>
=> fpga info
Altera Device
Descriptor @ 0x3ffec7a0
Family:         SoC FPGA
Interface type: Fast Passive Parallel (FPP)
Device Size:    4294967295 bytes
Cookie:         0x0 (0)
No Device Function Table.
=> fatls mmc 0:1
  6275664   zImage
            extlinux/
  7007204   soc_system.rbf
    25844   socfpga_cyclone5_kfb_dual_sdram.dtb

3 file(s), 1 dir(s)

=> oad mmc 0:1 ${loadaddr} soc_system.rbf;
Unknown command 'oad' - try 'help'
=> load mmc 0:1 ${loadaddr} soc_system.rbf;
7007204 bytes read in 363 ms (18.4 MiB/s)
=> fpga load 0 ${loadaddr} $filesize;
=>

And after the .rbf was loaded, the JTAG nodes showed up again when polled , through the NIOS shell with the USB Blaster:

~$ jtagconfig -n
1) USB-Blaster [1-4]
  4BA00477   SOCVHPS
  02D020DD   5CSEBA6(.|ES)/5CSEMA6/..
    Design hash    385F96C94BBA3F772A79
    + Node 0C206E00  JTAG PHY #0
    + Node 0C206E01  JTAG PHY #1
    + Node 0C206E02  JTAG PHY #2
    + Node 0C006E00  JTAG UART #0
    + Node 00486E00  Source/Probe #0

So, at this point, I have a functioning FPGA configuration loading when UBooting. Note this is with uncompressed bitstream files.

I guess the next thing that remains to check - is why and how to make the original attempt with compressed bitstream file (.rbf) to work :? 

Wow! I wasn't expecting that resolution!  Great job debugging, both of you! Board problems can be so difficult to find!

Sue