Forum Discussion
YoshiakiS_Altera
Occasional Contributor
1 day agoHello monkstein88,
The issue was happened on the following code.
https://github.com/altera-fpga/u-boot-socfpga/blob/socfpga_v2026.01/drivers/fpga/socfpga_gen5.c#L158
static int fpgamgr_program_poll_initphase(void)
{
unsigned long i;
/* Additional clocks for the CB to enter initialization phase */
if (fpgamgr_dclkcnt_set(0x4))
return -5;
/* (4) wait until FPGA enter init phase or user mode */
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
break;
if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
break;
}
/* If not in configuration state, return error */
if (i == FPGA_TIMEOUT_CNT)
return -6;
return 0;
}
This issue most likely is happened on the mismatch of MSEL and generated RBF, or Device OPN mismatch.
1) Check SOF. Please configure your SOF by Quartus Programmer via JTAG.
If it fails, Device OPN is incorrect. Please update DEVICE section in your qmtech_c5soc_kfb_dual_sdram_ghrd.qsf.
2) Check the compression mode of the RBF. Here are details of the settings.
|
MSEL |
Configuration Scheme |
Compression |
|
00000 |
FPPx16 |
Disabled |
|
01010 |
FPPx32 |
Enabled |
3) Check your power supply. Does the output current of your power supply meet requirement of the board?
Best regards,
Yoshiaki Saito