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monkstein88's avatar
monkstein88
Icon for Occasional Contributor rankOccasional Contributor
3 months ago
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A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected.

Hi Altera Comunity et al,   I guess this is more of a question for the support and moderator people of this forum. The situation is I just posted a topic explaining a problem I am experiencing with ...
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  • monkstein88's avatar
    monkstein88
    3 months ago

    Hello Yoshiaki,

    Thank you so much for taking the effort to test the .rbf files I built and shared  on your own DE10-Nano system, and confirming them that they actually work. :)

    On my side, on my own QMTECH board, I did the check (performed the register read from U-Boot shell) of  the 'stat' register of the FPGA Manager Module, and I think I found my answer/reason for my troubles. So I had set MSEL SW to '01010' (ON-OFF-ON-OFF-ON) on my board, stopped at U-Boot, issued the command and got the below:

    => md ff706000 1
ff706000: 00000058                             X...
=>

      So, I do NOT get the expected: 'ff706000: 00000050 P...'  , but actually 'ff706000: 00000058 X...' . And then I checked my board physically , toggling one pin at a time , and then reading back the 'stat'  register after each pin change.  And it was found out that one of the pad pins (the PIN.5) of the DIP SW was broken. And toggling the one switch adjacent to that pin, made no change in the 'stat' register readout. 

    So, I think the cause had been found for why Uboot can't load compressed .rbf succesfully - my board has a broken MSEL DIP SW pin and it just physically cannot apply/provide the MSEL = '01010'.  So, I have to fix my board in this case. 

    Anyway, at this point, I think the issue is to be considered SOLVED. You can close this ticket. 

    Much gratitutes Yoshiaki, you've been of great help!

    Best Regards,

    - Monk M.

YoshiakiS_Altera's avatar
YoshiakiS_Altera
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

Hello monkstein88,

The issue was happened on the following code.

https://github.com/altera-fpga/u-boot-socfpga/blob/socfpga_v2026.01/drivers/fpga/socfpga_gen5.c#L158

static int fpgamgr_program_poll_initphase(void)
{
    unsigned long i;

    /* Additional clocks for the CB to enter initialization phase */
    if (fpgamgr_dclkcnt_set(0x4))
        return -5;

    /* (4) wait until FPGA enter init phase or user mode */
    for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
        if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
            break;
        if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
            break;
    }

    /* If not in configuration state, return error */
    if (i == FPGA_TIMEOUT_CNT)
        return -6;

    return 0;
}

This issue most likely is happened on the mismatch of MSEL and generated RBF, or Device OPN mismatch.

1) Check SOF. Please configure your SOF by Quartus Programmer via JTAG.

If it fails, Device OPN is incorrect. Please update DEVICE section in your qmtech_c5soc_kfb_dual_sdram_ghrd.qsf.

2) Check the compression mode of the RBF. Here are details of the settings.

MSEL

Configuration Scheme

Compression

00000

FPPx16

Disabled

01010

FPPx32

Enabled

3) Check your power supply. Does the output current of your power supply meet requirement of the board?

Best regards,

 Yoshiaki Saito