Agilex 5E - PCIE PERST# pin - failing compilation

Hello! I'm using Critical Link MytiSom Dev Kit. It has the same FPGA as the Altera Dev Kit - A5ED065BB32AE6SR0. I'm adapting the PCIe Root Port example from Altera - I have assigned the PCIe Gen3x4 lanes to bank 4B. I have checked the pin assignments several times but I keep getting failed compilation with the error attached bellow. Any suggestions on what can cause the issue. I have also attached the pin assignments.

Thank you