Agilex 5E - PCIE PERST# pin - failing compilation

Thank you both for your reply. 

I have carefully placed the PCIe RX/TX pins and used the corresponding p0_pin_perst_n_i and p0_pin_perst_n_i_1, but I might have made wrong connections in the QSYS. I have copied the Altera PCIe_subsys, it is then connected to pcie_clk_rst_subsys, pcie_gts_rst (for the system PLLs on the side of the PCIe), the 100 MHz clk reset, the 250 MHz clk reset which are synchronized in the top_wrapper.sv in the example design and are now synced on my top. Are all these needed? The wrapper contains also rst_ctrl. It seems to me that this is the place were something might get tangled because I have not connected the perst_n pins to anything else, but the corresponding inputs in the pcie_subsys