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eharalanova's avatar
eharalanova
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4 months ago

Agilex 5E - PCIE PERST# pin - failing compilation

Hello! I'm using Critical Link MytiSom Dev Kit. It has the same FPGA as the Altera Dev Kit - A5ED065BB32AE6SR0. I'm adapting the PCIe Root Port example from Altera - I have assigned the PCIe Gen3x4 l...
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KelvinK_Altera's avatar
KelvinK_Altera
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3 months ago

Hi eharalanova​,

I would suggestion you to,

Check the Critical Link MitySom Dev Kit board schematic for the the Pin and IO 
Make sure have the pin assign in the correct bank and correct voltage.
Ex. Altera Agilex 5 Premium Devkit  using 3.3v for PERST.

Try to refer to the Critical Link guide on PCIe example design 

https://support.criticallink.com/redmine/projects/mitysom_a5/wiki/Mitysom-a5e-pcie-gen3x4-ep

If you have more details share here with us.