Stratix 10 HPS LED example

After selecting the HPS peripheral in the auto place IP, the HPS pins come up in the top level instantiation.

These HPS pins eg. SDMMC, USB etc which are part of HPS show up in the FPGA pin planner.  But not able to assigne any location to it. How do the locations get assigned to these dedicated HPS pins.

How to upload report files. it dosnot allow me to upload the file.

Iam using HPS and hard EMI for DDR4. Do i have to assign pin for DRR4 or will the quatrus auto assigne it.

Regarding the attachment, I have rechecked it. Please kindly rename the .rpt file to .txt before uploading.

I can attach a zip file. 

Stratix® 10 devices use a Secure Device Manager (SDM) to control both FPGA configuration and HPS boot. As part of this architecture, .pof files are not used. Instead, the device is programmed using .rbf (Raw Binary File) images, which can includes the HPS bootloader.

You may get the precompiled first stage bootloader (FSBL) .hex from here:
https://releases.rocketboards.org/2026.04/emmc/s10_htile_emmc/u-boot-spl-dtb.hex
This bootloader is generated as part of the Yocto-based GSRD build flow. For more details on how it is built, refer to: https://altera-fpga.github.io/rel-26.1/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/ 

If you prefer to build the bootloader manually, you can follow this guide: https://altera-fpga.github.io/rel-26.1/embedded-designs/stratix-10/sx/soc/boot-examples/ug-linux-boot-s10-soc/ 

The steps to include the bootloader into the .sof are documented here: https://docs.altera.com/r/docs/683847/26.1/stratix-10-soc-fpga-boot-user-guide/creating-the-configuration-files 

Example, if you have a HPS boot first design and configures via JTAG:

quartus_pfg -c design.sof design.rbf -o hps_path=fsbl.hex -o hps=on

For QSPI boot, you can follow this guide: https://altera-fpga.github.io/rel-26.1/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/#boot-from-qspi 

A detailed description of the boot flow is available here: https://docs.altera.com/r/docs/683847/26.1/stratix-10-soc-fpga-boot-user-guide/boot-flow-overview 

At a high level:
1. SDM reads the configuration image (e.g., from QSPI, SD, EMMC, or JTAG)
2. SDM loads the FSBL into HPS on-chip RAM
3. HPS starts executing the FSBL
4. FSBL initializes DDR and loads the next-stage bootloader (SSBL / U-Boot)

For SDM-based devices:
No additional RAM for the HPS needs to be added in the FPGA fabric

Once the RBF is loaded, the FSBL runs from HPS OCRAM, and the rest of the boot sequence proceeds from there.

Hi Sajeev_antony,

What you see

• Cold power-on → U-Boot → Linux starts → abrupt restart ~5 s into kernel (no panic text)
• Second boot succeeds to Linux; no further restarts until next power cycle
• SPL reports Reset state: Cold after the restart

Two plausible cause:

• First-power-on reset race (FPGA/SDM/board timing) — fits “once per power-on, second try OK at same kernel point”
• Watchdog — U-Boot starts watchdog@ffd00200 (10 s); Linux must take over. On S10, WDT timeout can be configured as cold reset, so “Cold” does not rule WDT out. But ~5 s kernel time and identical second-pass timing make a simple 10 s timeout less convincing.

How to prove it:

• After the spurious restart, at U-Boot: md.l 0xffd11000 1 (rstmgr status). Compare to intentional wdt expire.
• One trial: wdt stop before bootm. If double-boot disappears → WDT involved; if not → look at FPGA/SDM/cold reset path.

Fix direction (after proof):

• If WDT: hand over to Linux (enable driver + service it), or stop in U-Boot only until Linux owns it — do not leave WDT off permanently.
• If FPGA/SDM: fix first-boot sequencing (config/bridges/nCONFIG/power) before HPS runs application software. refer: https://docs.altera.com/r/docs/683222/25.3.1/stratix-10-hard-processor-system-technical-reference-manual/signal-behavior-event-diagrams