New Contributor
New ContributorRegarding the attachment, I have rechecked it. Please kindly rename the .rpt file to .txt before uploading.
I can attach a zip file.
New ContributorFitter report attached.
Also can you help me to get started with the GSRD. How to generate the Quartus project from the GSRD. Coun't find any Quartus project file in it.
New ContributorYou may kindly refer this latest fitter report file from Quartus 26.1
New Contributorthank you for the report.
Based on the report, you can search for “I/O Assignment Warnings”, which should provide relevant details. A sample snippet is shown below for reference.
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Assignment Warnings ;
+--------------------------+--------------------------------------------------------------------------------------------------------------------+
; Pin Name ; Reason ;
+--------------------------+--------------------------------------------------------------------------------------------------------------------+
; hps_usb_uart_tx ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ;
; hps_spim0_CLK ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ;
; hps_spim0_MOSI ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ;
; hps_spim0_SS0_N ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ;
; hps_spim0_SS1_N ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ;
; hps_usb1_STP ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ;
; hps_sdmmc_clk ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ;
; fan1_pwm ; Missing drive strength and slew rate on output pin, a default slew rate value of 1 has been used ;
; fan2_pwm ; Missing drive strength and slew rate on output pin, a default slew rate value of 1 has been used ;You may refer to the following guide for configuring the I/O standard: https://docs.altera.com/r/docs/683518/24.3/stratix-10-general-purpose-i/o-user-guide/stratix-10-i/o-overview
From the report, I also noticed that the fitter has assigned the EMIF pins (example shown above). However, I would recommend cross-checking these assignments against your board schematic to ensure correctness.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+--------------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+------------+---------------+----------+--------------+-------------------------+------------------+-----------------------------------+---------------------------------------------------------------------------------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+--------------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+------------+---------------+----------+--------------+-------------------------+------------------+-----------------------------------+---------------------------------------------------------------------------------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; board_leds[0] ; A39 ; 2K ; 61 ; 156 ; 61 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8-V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
; board_leds[1] ; B36 ; 2K ; 61 ; 155 ; 61 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8-V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
; board_leds[2] ; B37 ; 2K ; 61 ; 154 ; 61 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8-V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
; board_leds[3] ; B39 ; 2K ; 61 ; 153 ; 61 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8-V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
; ddr4_emif_mem_a[0] ; F28 ; 2M ; 61 ; 220 ; 31 ; no ; no ; 1 ; no ; yes ; no ; Off ; SSTL-12 ; Default ; Series 34 Ohm with Calibration ; u0|emif_s10_hps_0|emif_s10_hps_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; no ; Fitter ; - ; - ;
; ddr4_emif_mem_a[10] ; A29 ; 2M ; 61 ; 230 ; 31 ; no ; no ; 1 ; no ; yes ; no ; Off ; SSTL-12 ; Default ; Series 34 Ohm with Calibration ; u0|emif_s10_hps_0|emif_s10_hps_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; no ; Fitter ; - ; - ;
; ddr4_emif_mem_a[11] ; A28 ; 2M ; 61 ; 231 ; 31 ; no ; no ; 1 ; no ; yes ; no ; Off ; SSTL-12 ; Default ; Series 34 Ohm with Calibration ; u0|emif_s10_hps_0|emif_s10_hps_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; no ; Fitter ; - ; - ;
; ddr4_emif_mem_a[12] ; B26 ; 2M ; 61 ; 223 ; 46 ; no ; no ; 1 ; no ; yes ; no ; Off ; SSTL-12 ; Default ; Series 34 Ohm with Calibration ; u0|emif_s10_hps_0|emif_s10_hps_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; no ; Fitter ; - ; - ;
; ddr4_emif_mem_a[13] ; B27 ; 2M ; 61 ; 224 ; 46 ; no ; no ; 1 ; no ; yes ; no ; Off ; SSTL-12 ; Default ; Series 34 Ohm with Calibration ; u0|emif_s10_hps_0|emif_s10_hps_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; no ; Fitter ; - ; - ;
; ddr4_emif_mem_a[14] ; A27 ; 2M ; 61 ; 225 ; 46 ; no ; no ; 1 ; no ; yes ; no ; Off ; SSTL-12 ; Default ; Series 34 Ohm with Calibration ; u0|emif_s10_hps_0|emif_s10_hps_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; no ; Fitter ; - ; - ;You can find the 26.1 Quartus project at the following link: s10_soc_htile_devkit_emmc_QPDS-26.1pro.zip https://releases.rocketboards.org/2026.04/emmc/s10_htile_emmc/
This is the same .zip package that I previously attached.
To regenerate the project, you can follow the steps here:
git clone https://github.com/altera-fpga/stratix10-ed-gsrd.git
cd stratix10-ed-gsrd
git checkout QPDS26.1_REL_GSRD_PR
make s10-htile-soc-devkit-emmc-baseline-generate-design
cd s10_soc_devkit_ghrdAfter that, you can open the Quartus project: ghrd_1sx280hu2f50e1vgas.qpf
May i know if you are using stratix-10-sx-soc-development-kit or a custom board?
