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eharalanova's avatar
eharalanova
Icon for New Contributor rankNew Contributor
4 months ago

Agilex 5E - PCIE PERST# pin - failing compilation

Hello! I'm using Critical Link MytiSom Dev Kit. It has the same FPGA as the Altera Dev Kit - A5ED065BB32AE6SR0. I'm adapting the PCIe Root Port example from Altera - I have assigned the PCIe Gen3x4 l...
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RongY_altera's avatar
RongY_altera
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3 months ago

Hi,

The error message points to your pcie_perst_n.

 

Please make sure you don't use this pin for other purpose in your design. Then confirm the pin location and voltage in your qsf. Below are the settings from Agilex5 Modular Dev Kit FYR. 

set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to p0_pin_perst_n_i_reset_n
set_instance_assignment -name WEAK_PULL_DOWN ON -to p0_pin_perst_n_i_reset_n

 

 

Regards,

Rong