Forum Discussion
Occasional ContributorA topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected.
Hello Yoshiaki,
Thank you so much for taking the effort to test the .rbf files I built and shared on your own DE10-Nano system, and confirming them that they actually work. :)
On my side, on my own QMTECH board, I did the check (performed the register read from U-Boot shell) of the 'stat' register of the FPGA Manager Module, and I think I found my answer/reason for my troubles. So I had set MSEL SW to '01010' (ON-OFF-ON-OFF-ON) on my board, stopped at U-Boot, issued the command and got the below:
=> md ff706000 1 ff706000: 00000058 X... =>So, I do NOT get the expected: 'ff706000: 00000050 P...' , but actually 'ff706000: 00000058 X...' . And then I checked my board physically , toggling one pin at a time , and then reading back the 'stat' register after each pin change. And it was found out that one of the pad pins (the PIN.5) of the DIP SW was broken. And toggling the one switch adjacent to that pin, made no change in the 'stat' register readout.
So, I think the cause had been found for why Uboot can't load compressed .rbf succesfully - my board has a broken MSEL DIP SW pin and it just physically cannot apply/provide the MSEL = '01010'. So, I have to fix my board in this case.
Anyway, at this point, I think the issue is to be considered SOLVED. You can close this ticket.
Much gratitutes Yoshiaki, you've been of great help!
Best Regards,
- Monk M.
Occasional ContributorThen, I took the .rbf file (from the prev post) and put in (overwriting the older .rbf file) to the FAT partion of the SD Card, and set the MSEL [4:0] = '00000' (All are 'ON' ) , and powered up the board. And this time there were no errors when loading the .rbf.
U-Boot SPL 2024.07-36780-g67806ba5853-dirty (May 09 2026 - 16:08:17 +0300)
Trying to boot from MMC1
U-Boot 2024.07-36780-g67806ba5853-dirty (May 09 2026 - 16:08:17 +0300)
CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC Internal Transceiver (3.0V)
DRAM: 1 GiB
Core: 29 devices, 15 uclasses, devicetree: separate
MMC: dwmmc0@ff704000: 0
Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Model: QMTECH C5SOC KFB Dual SDRAM
Net:
Error: ethernet@ff702000 No valid MAC address found.
No ethernet found.
Hit any key to stop autoboot: 0
=>
=> fpga info
Altera Device
Descriptor @ 0x3ffec7a0
Family: SoC FPGA
Interface type: Fast Passive Parallel (FPP)
Device Size: 4294967295 bytes
Cookie: 0x0 (0)
No Device Function Table.
=> fatls mmc 0:1
6275664 zImage
extlinux/
7007204 soc_system.rbf
25844 socfpga_cyclone5_kfb_dual_sdram.dtb
3 file(s), 1 dir(s)
=> oad mmc 0:1 ${loadaddr} soc_system.rbf;
Unknown command 'oad' - try 'help'
=> load mmc 0:1 ${loadaddr} soc_system.rbf;
7007204 bytes read in 363 ms (18.4 MiB/s)
=> fpga load 0 ${loadaddr} $filesize;
=>And after the .rbf was loaded, the JTAG nodes showed up again when polled , through the NIOS shell with the USB Blaster:
~$ jtagconfig -n
1) USB-Blaster [1-4]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..
Design hash 385F96C94BBA3F772A79
+ Node 0C206E00 JTAG PHY #0
+ Node 0C206E01 JTAG PHY #1
+ Node 0C206E02 JTAG PHY #2
+ Node 0C006E00 JTAG UART #0
+ Node 00486E00 Source/Probe #0So, at this point, I have a functioning FPGA configuration loading when UBooting. Note this is with uncompressed bitstream files.
I guess the next thing that remains to check - is why and how to make the original attempt with compressed bitstream file (.rbf) to work :?
