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Motaz_sami's avatar
Motaz_sami
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17 hours ago

U-Boot "Synchronous Abort" boot failure on Terasic Atum A5 Rev B via Quartus 24.3 .jic generation

I am reaching out for technical assistance regarding a reproducible boot failure on the Terasic Atum A5 Rev B development board (Agilex 5) when using Quartus Prime Pro 24.3.

I am attempting to compile a custom design that utilizes the Lightweight HPS-to-FPGA (lwhps2fpga) bus. My current workflow is as follows:

Compile the project in Quartus 24.3 to generate the .sof file.

Merge the .sof with the official Terasic FSBL .hex file.

Use the Programming File Generator (PFG) to create a .jic file.

Flash the .jic to the QSPI.

The Issue:

When flashing the .jic generated by this workflow, the boot process fails during the main U-Boot phase. The U-Boot SPL and ATF (BL31) load successfully. However, after U-Boot attempts to load the environment, the system crashes with a "Synchronous Abort" handler (esr 0x96000010, far 0x108d2000). This triggers a CPU reset with the message ### ERROR ### Please RESET the board ###.  

(I have attached the full UART terminal log of the boot sequence for reference).

Isolation Testing:

To isolate the issue from my custom logic, I applied this exact same compilation and .jic generation workflow to the official Terasic GHRD bundled with the board. The result was identical—the GHRD .jic generated by Quartus 24.3 crashes at the exact same U-Boot Synchronous Abort.

Conversely, when I bypass compilation and simply flash the original, pre-compiled .jic provided in the Terasic resource package, the board boots into Linux flawlessly. This confirms the physical hardware is fully functional and the issue is strictly isolated to the .jic files being generated by the 24.3 workflow.

Questions:

Is there a known issue or missing step in the Quartus 24.3 workflow when merging the FSBL or configuring the .jic for the Agilex 5 that would cause U-Boot to encounter a Data Abort (likely when probing the AXI bridges)?

What are the exact PFG parameters or required patches to successfully generate a booting .jic for this board under the 24.3 release?

I look forward to your guidance on resolving this workflow issue

Arm Processor
general
Hps Boot

1 Reply

  • JamesG_Altera's avatar
    JamesG_Altera
    Icon for New Contributor rankNew Contributor
    10 hours ago

    I have some questions about the process you have followed:

    • What command did you use to merge the .hex with the SOF? Did you use the command found in sof_with_hps.bat supplied by Terasic?
    • What command did you use to generate the JIC file from the SOF? Did you use the command found in sof_to_jic.bat supplied by Terasic?
    • Your U-boot SPL comes from the hex file supplied by Terasic, in the GHRD source tree. But where does your full U-Boot software come from?