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New Contributor

2 months ago

U-Boot "Synchronous Abort" boot failure on Terasic Atum A5 Rev B via Quartus 24.3 .jic generation

I am reaching out for technical assistance regarding a reproducible boot failure on the Terasic Atum A5 Rev B development board (Agilex 5) when using Quartus Prime Pro 24.3. I am attempting to compi...

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Contributor

1 month ago

Hi Motaz_sami,

Thanks for posting your solution. That is super helpful to the community.

Please review these examples:

https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/documentation/01_index.md

There are a couple in there that enable the bridges.

Sue

JamesG_Altera

New Contributor

1 month ago

Hi Motaz_sami,

Were you able to review the examples that Sue provided? Have you been able to make progress with the bridges?

Best Regards,

James Grant

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U-Boot "Synchronous Abort" boot failure on Terasic Atum A5 Rev B via Quartus 24.3 .jic generation

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