Preloader/U-Boot Compilation Failure

Hi IOzan​ ,

Could you let me know which version of the tool you are using?
Also, could you share the log text from the make command—including the exact error messages you are seeing?

Thank you,
Sho

Hi IOzan ,

On top of Sho comments, could you also tell us also about the software version that you're using (eg. uboot, Quartus etc) ?

Thanks.

Regards

Kian

First, thank you very much for your quick response!

Below are the software versions I'm using on my standalone laptop:

• Quartus Prime: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
• SoC EDS Command Shell: Version 18.1 [Build 625]

Note One (From the log file)

According to the log file, the system initially searches for the file uboot-socfpga.tar.gz inside the intelFPGA/18.1 installation directory. This is strange because I'm working with the lite vision… I moved the file into the project directory and updated the Makefile accordingly which resulted in the rest of the log entries as shown in the attached file.

Note: I have a second computer (network license) with the following version:

• Quartus Prime: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition

However, that machine does not have the SoC EDS installed.

Would it be helpful if I purchased additional add-ons for the internal network computer and performed the process there instead? Do you think that would resolve the issue? If so, what add-ons should i purchase? What can I do to continue the process in my stand alone lite computer? 

Hi IOzan​ ,
Thank you for sending the tool information, your work details, and the error logs.

First, I would like to note that the version you are using, 18.1std, has already reached the end of support, and it is recommended to use the latest version, 25.1std.

(However, I understand that there may be cases where you need to use this older version for various reasons...)
I believe the root cause of the issue you are facing is that an error is occurring in the tar command.
   tar: Error opening archive: Failed to open '/cygdrive/c/intelFPGA/....'

To address this root cause, please try modifying the Makefile as follows:
1. Re‑generate the spl_bsp folder and start from the original Makefile.
2. On the line following line 93, which contains ifeq ($(HOSTOS),cygwin), add the following one line:
   UNTAR := $(SOCEDS_DEST_ROOT)/host_tools/cygwin/bin/tar zxf

Then run make.

This modification does not change the value of the TGZ variable; rather, it explicitly forces the build process to use the tar command installed in the SoC EDS Cygwin environment.

Please let me know if this Makefile modification resolves the issue.

Thanks,
Sho

Hi, thanks again!

I added line 94 and the file started compiling—the fix definitely helped.

However, at the end of the compilation process, I received some other errors. I’ve attached the execution log.

What do you think could be the cause? Do you think the problem might be is vision and/ or licenses? if so, do you think it would help if I download an up-to-date evaluation version (30 days)? (so if it works, I will know exactly what to purchase). 

Thanks a lot, 

Idan

Hi,

Thank you so much for your patience and your help- I'm really not sure how to solve this. 

It's now running in administrator... :)- still failing (see attached log).

Idan

Hi IOzan​ ,

So, the 'sed: cannot rename .../sedXXXXXX: Permission denied' error still occurs after all.

Since this error is typically caused by environment‑specific factors within the Cygwin layer on Windows — such as file‑locking behavior, antivirus interference, or permission propagation — it is hard to offer a certain solution, unfortunately.

That said, try a few additional tests ?
Create a new spl_bsp directory in a location where you have full read/write permissions, preferably in a new folder on C: drive, and run make. Does this attempt generate exactly the same error log?  (Try this several times.)

( Alternatively, you might consider abandoning Cygwin on your Windows environment and building it in a Linux environment instead.... )

Thanks,
Sho