General Background: I'm working with a custom board that has an Altera/Intel Cyclone V, SoC FPGA (5CSEBA6U23, similar to the DE10-Nano development kit). The board is already equipped with all the n...
Hi IOzan , Thank you for sending the tool information, your work details, and the error logs.
First, I would like to note that the version you are using, 18.1std, has already reached the end of support, and it is recommended to use the latest version, 25.1std.
(However, I understand that there may be cases where you need to use this older version for various reasons...) I believe the root cause of the issue you are facing is that an error is occurring in the tar command. tar: Error opening archive: Failed to open '/cygdrive/c/intelFPGA/....'
To address this root cause, please try modifying the Makefile as follows: 1. Re‑generate the spl_bsp folder and start from the original Makefile. 2. On the line following line 93, which contains ifeq ($(HOSTOS),cygwin), add the following one line: UNTAR := $(SOCEDS_DEST_ROOT)/host_tools/cygwin/bin/tar zxf
Then run make.
This modification does not change the value of the TGZ variable; rather, it explicitly forces the build process to use the tar command installed in the SoC EDS Cygwin environment.
Please let me know if this Makefile modification resolves the issue.