Linux mSGDMA Driver Agilex 5
I am trying to use stream-to-memory DMA to move data. This is the design, showing the important Quartus connections: Which corresponds to this address config: # address map write_sdram = 0x00000000 read = NULL (has no meaning in streaming to MM mode) msgdma_csr = 0x22000040 msgdma_descriptor = 0x22000060 # msgdma offsets msgdma_csr_control = 0x4 + 0x22000040 = 0x22000044 msgdma_descriptor_write_low = 0x4 + 0x22000060 = 0x22000064 msgdma_descriptor_length = 0x8 + 0x22000060 = 0x22000068 msgdma_descriptor_control = 0xc + 0x22000060 = 0x2200006c The oscillator IP generates a group of known numbers, so the readbacks change each time - but are predictable and so the hardware is verifiable. In U-Boot; I have verified that this design. This script asks the DMA to make two transfers, and reads back the results each time. SOCFPGA_AGILEX5 # mw 0x22000044 0x1 # Stop Dispatcher SOCFPGA_AGILEX5 # mw 0x22000044 0x20 # Stop descriptors SOCFPGA_AGILEX5 # mw 0x22000044 0x2 # Reset Dispatcher SOCFPGA_AGILEX5 # mw 0x22000064 0x00000000 # Write address SOCFPGA_AGILEX5 # mw 0x22000068 0x8 # Write length in bytes SOCFPGA_AGILEX5 # md 0x22000040 1 # Check status 22000040: 00000002 .... SOCFPGA_AGILEX5 # mw 0x2200006c 0x02000000 # Wait for response SOCFPGA_AGILEX5 # sleep 1 SOCFPGA_AGILEX5 # mw 0x2200006c 0x82000000 # execute SOCFPGA_AGILEX5 # md 0x22000040 1 # Check status 22000040: 00000002 .... SOCFPGA_AGILEX5 # md 0x00000000 1 # read 00000000: 00000000 .... SOCFPGA_AGILEX5 # mw 0x22000044 0x2 # reset SOCFPGA_AGILEX5 # mw 0x2200006c 0x82000000 # execute SOCFPGA_AGILEX5 # md 0x00000000 1 # read 00000000: 67676767 .... When trying to do the same in linux using 'devmem2', I found that the readbacks did not change, so I decided to look for some examples. I found this stream-to-mapped mSGDMA driver built for the Cyclone V, and so re-purposed it. The driver example above both reads and writes to the device using the ‘dd’ utility in linux, but I am for now only interested in the read command. To do so I needed some information... Based on the .qsys design file output of my project, the mSGDMA block generates this interrupt: ... <altera:connection altera:kind="interrupt" altera:version="24.3" altera:start="subsys_hps.f2h_irq0_in" altera:end="msgdma_0.csr_irq"> <altera:connection_parameter altera:parameter_name="irqNumber" altera:parameter_value="2"> </altera:connection_parameter> </altera:connection> ... And according to the interrupt docs, the above csr interrupt value=2 maps to the GIC interrupt 51, which is 19 when referenced from the linux device tree. With this information, I have defined the following mSGDMA element in the .dts: ... msgdma_test: msgdma_test@22000000 { compatible = "msgdma_test"; reg = <0x0 0x22000000 0x0 0x100>; interrupt-parent = <&intc>; interrupts = <0 19 4>; }; ... Which only differs from the original in that it has a different interrupt number, and different base address - also accounting for the lwhps2fpga offset, due to it being the Agilex5 and not the Cyclone. The driver code from the REDS blog post has also been edited in the following way: I need to change a deprecated function in the main driver code: devm_ioremap_nocache to demv_ioremap. I want to see the data which has been moved - to do so have added an info print to the msgdma_read method: printk(KERN_INFO "MSGDMA: Read buffer content: %.*s\n", (int)read_ret, (char*)data->dma_buf_rd); There is only 1 interrupt, so we set data->msgdma1_irq = platform_get_irq(pdev, 0); Since there is no ability coded to fabric to perform msgdma_write - we can also remove memory allocations, remaps and references to msgdma0 and other write related objects. I think the following shows that the DMA is firing interrupts, and so I am confident that I have connected the correct interrupt: cat /proc/interrupts | grep msgdma 50: 2 0 0 0 GICv3 51 Level msgdma1 However, when looking at the kernel outputs after requesting reads via dd: $ dd if=/dev/msgdma_test of=/dev/null bs=8 count=1 $ dmesg | tail [ ... ] MSGDMA: Read buffer (hex): 00 00 00 00 00 00 00 00 [ ... ] MSGDMA: Read buffer (hex): 00 00 00 00 00 00 00 00 The driver code in question is included in msgdma.c and header_msgdma.c, attached to the post (This forum does not seem to like .h files...) I was hoping someone might have an idea of where I went wrong! Any helpers are much appreciated! Thanks for your time, K
Sending serial commands on DB9 Arria 10 SoC FPGA
I am attempting to send serial based commands using the RS-232 protocol on the DB9 connector on the Arria 10 but do not know which device to use within my C program. I've opened "/dev/tty0" and can send appropriate commands "AT+CGMM\r" but these commands are sent out the J10 UART1 (HPS) on the board and not the DB9. I'm unable to read "/dev/ttyS1" within my c program. I've tried various other devices without luck. I've also set status to "okay" on serial0@ffc02000. In file: ./arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts and rebuild the dtb and placed on SD card. I've looked in Non-8250 serial port support in .config but haven't modified the kernel. Previously, I did enable the FTDI in the kernel for another device and got that working correctly. Any suggestions will be greatly appreciated. Thank you. stty -F /dev/ttyS1 stty: /dev/ttyS1: Input/output error
Arria 10 SoC Dev Kit Baremetal HPS examples issue & workflow
Hi, I recently acquired an Arria 10 SoC dev kit but I'm really struggling to run either the examples on embedded-software/bare-metal or the ones included in SoC EDS pro 20.1, trying to follow the instructions for both of them, they seem to rely on a old version of SoC EDS which included within ARM DS-5 and the toolchain, but now SoC EDS & ARM DS are separated and I cannot build the examples. With the new applications the flow for using this examples should remain the same? I mean: use Pogrammer to program the included .sof inside ghrd (or generate a updated one) -> open ARM-DS from SoC-EDS with environmental variables assigned and build with new toolchain arm-none-eabi -> run from ARM-DS (can i without license?) Seems like most of the tools used for running this examples have been discontinued (for example ) so at this point I don't know which workflow should I actually follow. PD: finally I was able to generate de application.axf from this example Altera-SoCFPGA-HardwareLib-16550-CV-GNU with an old toolchain but I don't know how to program it without a license, for now I don't want to debug anything, just do some simple tests printing by uartAgilex 5 HPS TEE
Hi, Is Arm Trust Zone supported on HPS? If so is the implementation of TEE supported on Agilex 5? I've checked TF-A sources and it seems that BL2 on this platform loads only BL31 and BL33. How about BL32? Is there an OP-TEE support? If not, are there any plans to provide it in the nearest feature?
To evaluate and monitor CPU frequency behavior in the Kernel OS
We need to verify CPU frequency behaviour straight from the Linux kernel because we are currently working with a customised Agilex 5 System-on-Module (SOM). Ensuring appropriate frequency scaling and governor functionality under a range of workloads is our aim. Would you kindly provide guidance regarding the device tree modifications, kernel configurations, and testing methods needed to enable and validate CPU frequency scaling on this platform? I would be very grateful for any advice or reference materials that are specific to Agilex 5.Validating ECC Functionality on Custom Agilex 5 SOM in Linux Kernel
We are now looking to validate ECC (Error Correction Code) functionality on our custom Agilex 5 System-on-Module (SOM) running Linux. Our objective is to ensure that ECC is correctly enabled and functioning across all relevant memory regions, and that error detection and correction mechanisms are properly integrated at the kernel level. Could you please provide guidance on the necessary kernel configurations, device tree modifications, and available tools or procedures to test and monitor ECC behavior on this platform? Any documentation or reference designs specific to Agilex 5 ECC support would be highly valuable.25.3 PRO Release
Version: Release 25.3 PRO Quartus Build/TAG: B109/QPDS25.3_REL_GSRD_PR Release Date: October 10, 2025 Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7, Startix® 10, Arria® 10 Release Type: Major release/Binary release Binary Release Path: http://releases.rocketboards.org/2025.10/ Major Features Released Support of GHRD 2.0 in Agilex™ 5 which includes foundational boot to Linux, ability to create compatible phase 2 bitstreams, parameterized HPS for maximum performance and best practices. Support of GSRD 2.0 Yocto layers for the Agilex 5 E-Series Premium DevKit with OOBE daughtercard for the GHRD 2.0 baseline design. Agilex 5 GSRD Development User Experience Improvement through KAS using a graphical/text interface to configure a limited number of high-level options on top of simplified Yocto recipes. - GSRD 2.0 with Kas Build System Support for running Agilex 5 Simics Simulation under the GSRD 2.0 framework. Booting from SD Card and QSPI is supported. - Exercising Simics Simulation from GSRD 2.0 Support GHRD and GSRD for Agilex™ M-Series PRQ HBM2e for DK-Sl-AGM039EA development kit. The GSRD is capable of booting to Linux. - Build the GSRD for DK-DEV-AGM039EA Hypervisor Multi-OS Support Example, demonstrating Linux and Zephyr running side-by-side in the HPS cluster. - HPS Xen Hypervisor GSRD System Example Design: Agilex™ 3 FPGA and SoC C-Series Development Kit Support for monitoring of SEU errors from the SDM in the HPS in Agilex™ 7. Add capability to measure the latency of Linux SMC calls. Support Nios V Lockstep application with a fail-safe mechanismUnable to access rocketboards.org
Hi, I am currently unable to access the www.rocketboards.org website. I need it for multiple purposes related to the use of the GSRD for cyclone 5, namely it is accessed by the image build script. Any information as to why the website is no longer working and when it might be available again? Thanks!
