Stratix 10 Linux SD card booting
Hi Altera Community, I tried multiple attempts to boot the SD card from Rocketboard.org. https://releases.rocketboards.org/ I downloaded and booted the SD card with the .wic image file. It only has the .itb file by default in the boot partition. Whenever I try to boot, it asks for the U-Boot.img file. And also it says "failed to load "socfpga_stratix10_socdk.dtb" even if the file is there. And then I compiled my simple HPS design and can easily program the FPGA from the Quartus Programmer (rbf and sof file), but whenever I try to overlay it, like say: echo overlay.dtb > /sys/kernel?config?device-tree/overlays/0/path It says "FPGA manager error, timeout," and so on. Does any community member have notes or steps that you made to boot the SD card of the Stratix 10 FPGA? I am following this link: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderStratix10
S10 hps fpga2sdram bridge low speed
Hello, i have some problems I have a project with stratix 10 with hps I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width Via u-boot smc configured and enabled them, but measured speed is not enough. When I use onle one bridge my speed is approximately 32 gbit/s (bridge and master frequency 350 MHz) But when I use all 3 bridges it becomes 20 gbit/s I use avmm bridge to connect to axi fpga2sdram bridge with 128 bits width, max pending writes 16, max burst size 128, use only write to bridge ECC in emif (hmc) is disabled I tried to use QoS for bridges, set them to bypass P.S. If i use the same board with firmware without hps, i get 130 gbit/s (with disabled hps) Quartus Pro 21.4 Any help would be useful!
Timings eMMC
Hi, latest datasheet of SoC « 813918/2026.01.05 » lists in paragraph « HPS SD/eMMC Timing Characteristics » the constraints of eMMC, applicable to memory component but does not define any timing data in input/output of SoC. There is no Tco min/max of CMD/DATA at SoC output, as well as Tsetup/hold of CMD/DATA at SoC input. Can you provide Tco and Tsetup/hold for eMMC usage (Legacy, HS_SDR, HS_DDR, HS200, HS400) ? thanks
Support Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA
Hi Altera Support Team, Greetings from Logic Fruit Technologies. This is Bhanu Pratap and I am working on the project in which we are using Agilex-7 SOC FPGA. Goal: Utilize Agiliex-HPS's capability on a Linux OS to control dynamic features of IP Cores at runtime. Problem Statement: We are facing an issue detecting SignalTap with SoC-based designs for runtime debugging while it's enabled and added from the Quartus project to generate the programming file. Brief Description: We are using Quartus 2025.1.1 and Altera's Agilex-7 Devkit(DKSIAAGI027FA: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit -> 4x F-Tile, Rev C). We downloaded the base GHRD design from Altera's GitHub webpage for the corresponding Quartus version. We are following each step to test GHRD and build generation for the Linux OS. We are using HPS First booting mode, we generated the build without modification and tested it. It's working fine according to the GSRD user guide. We have added a custom AXI4 Slave based CSR module to the HSP Lightweight bus to test basic register read/write using Platform Designer. We regenerated the build and re-tested but we are not getting the expected results so we added SignalTap for debugging. Build is generated using the STP file, programmed, and the OS is booting but it's not detecting SignalTap. This looks more like a process gap. We seek your support to fix this issue. Note: If we use an FPGA design without HPS, we are able to add and detect SignalTap. Seeking for urgent support. Thanks Bhanu PratapAgilex 5 Premium Dev Kit Ethernet Performance
Hello! We built the golden sample image following the HPS GSRD User Guide with additional packages to profile/evaluate the board and experience performance problems when sending data over ethernet. The test setup is a host connected to the dev kit and sending data to test the throughput. First, we used iperf3 with zero copy flag, which caps at about 940 Mbit/s with almost no variation. Without zero copy, iperf3 caps at about ~880 Mbit/s with some variation down to 629 Mbit/s, see attachment 1.png. With our custom application that also does some additional work, we’d expect about 430-440 Mbit/s, but cap at about 300 Mbit/s, with lots of time spent in kernel again, see attachment 2.png. From the first investigation, we suspect the driver can’t keep up with the generated data and can’t send it fast enough to the host. We are wondering whether we can adjust something in the kernel (driver) or in the image so that we can improve the throughput with heavy workloads. Kind regards!
Agilex 5 HPS EMAC2 SWR bit in DMA_Mode Register Not Clearing
Hello, Following section 5.1.7 of the Agilex 5 Hard Processor System Technical Reference Manual, and based on what I found in U-Boot and Linux, I am writing an Ethernet driver that uses EMAC2 with an RGMII interface. I am currently stuck at the software reset using the SWR bit of the DMA_Mode register, as it remains set to 1. Our boot flow on the AXE5-Eagle board is ATF -> U-Boot -> our OS. We use the U-Boot from https://github.com/ArrowElectronics/u-boot-socfpga/tree/socfpga_v2025.07 with some adaptations to load our OS instead of Linux. When I read the DMA_Mode register before performing any EMAC setup in our OS, I already see the value set to 1. After bringing the PHY out of reset and setting the SWR bit again, it does not clear. I also tried putting the EMAC into reset using the per0modrst register, setting the System Manager tsn2 register to 1 again, and then bringing the EMAC out of reset. This did not help, and after resetting the EMAC I can no longer read PHY registers over MDIO. When I load Linux instead of our OS, I can see that the reset using the SWR bit works correctly, but I can’t find what is missing in my implementation. Any help would be greatly appreciated. Thanks, Sarah For additional context, I read the following values before putting the EMAC2 in reset: PHY ID1: 0x283 Main PLLGLOB: 35000103 Per PLLGLOB: 35000103 DMA_Mode: 00000001 SYSMGR_TSN2: 1 EMAC2_DWCXG_CORE_MAC_TX_CONF: 0 CLKMGR_PERPLL_EN: fffffff CLKMGR_PERPLL_BYPASS: 0 CLKMGR_PERPLL_EMACCTL: 0 CLKMGR_CTLGRP_EMACACTR: 10001 CLKMGR_CTLGRP_EMACPTPCTR: 0 CLKMGR_CTLGRP_EXTCNTRST: 0Agilex 5 HPS EMAC2 SWR bit in DMA_Mode Register Not Clearing
Hello, Following section 5.1.7 of the Agilex 5 Hard Processor System Technical Reference Manual, and based on what I found in U-Boot and Linux, I am writing an Ethernet driver that uses EMAC2 with an RGMII interface. I am currently stuck at the software reset using the SWR bit of the DMA_Mode register, as it remains set to 1. Our boot flow on the AXE5-Eagle board is ATF -> U-Boot -> our OS. We use the U-Boot from https://github.com/ArrowElectronics/u-boot-socfpga/tree/socfpga_v2025.07 with some adaptations to load our OS instead of Linux. When I read the DMA_Mode register before performing any EMAC setup in our OS, I already see the value set to 1. After bringing the PHY out of reset and setting the SWR bit again, it does not clear. I also tried putting the EMAC into reset using the per0modrst register, setting the System Manager tsn2 register to 1 again, and then bringing the EMAC out of reset. This did not help, and after doing this I can no longer read PHY registers over MDIO. When I load Linux instead of our OS, I can see that the reset using the SWR bit works correctly, but I can’t find what is missing in my implementation. Any help would be greatly appreciated. Thanks, Sarah For additional context, I read the following values before putting the EMAC2 in reset: PHY ID1: 0x283 Main PLLGLOB: 35000103 Per PLLGLOB: 35000103 DMA_Mode: 00000001 SYSMGR_TSN2: 1 EMAC2_DWCXG_CORE_MAC_TX_CONF: 0 CLKMGR_PERPLL_EN: fffffff CLKMGR_PERPLL_BYPASS: 0 CLKMGR_PERPLL_EMACCTL: 0 CLKMGR_CTLGRP_EMACACTR: 10001 CLKMGR_CTLGRP_EMACPTPCTR: 0 CLKMGR_CTLGRP_EXTCNTRST: 0
Why does the system report an error when generating rbf from sof files and fsbl files?
Error message: Error: Internal Error: Sub-system: BITASM, File: /quartus/pgm/bitasm/bitasm_common_code.cpp, Line: 518 HPS data start address(-1950584) is not 16 aligned Device and tool information： The device used is Stratix 10 1SX110HN2F43I2VG, without using the Stratix 10 SoC Development Kit； Quartus Prime Pro25.1.1 U-boot source code：u-boot-socfpga-socfpga_v2025.04 ATF source code：arm-trusted-firmware-socfpga_v2.13.0 Operation steps： Simplified the Platform Designer section of the Stratix 10 GHRD project； 【Device and Pin Options】->【Configuration】Set the HPS/FPGA configuration order to be HPS First； The Quartus full compilation generates the sof file in the "output_files" directory； Compile the ATF source code, and obtain the bl31.bin file in the path of ./build/stratix10/release； Copy the bl31.bin file to the root directory of u-boot, compile the u-boot source code, and obtain the u-boot-spl file in the ./spl/ directory； Convert u-boot-spl to u-boot-spl.hex and copy it to the output_files directory； Open the Programming File Generator tool and configure the Output Files： Configure Input Files, add sof and HEX files： 9. Configuration Device： 10. Generate error：
