HPS SDRAM Calibration Failed
To whom it may concern, The HPS of a Cyclone V SoC based board that I designed is failing the booting process. In which the following error message is outputted to the console: U-Boot SPL date and time SDRAM Calibration Failed. ERROR ### Please Reset the board ### I’m trying to determine the cause of the SDRAM calibration failure by enabling calibration reporting as indicated in: https://www.intel.com/content/www/us/en/docs/programmable/683841/17-0/enabling-the-debug-report-for-arria.html https://www.intel.com/content/www/us/en/docs/programmable/683841/17-0/determining-the-failing-calibration.html but I’m only getting the above mentioned message without an indication of the failing SDRAM stage and cause. please advise on how to get the preloader to output debug insights to the console. Please note that the approach described in the link below was used to create the Preloader: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10 Also, please advise on the sequence of failure messages that are outputted by the Preloader. Regards,
Cyclone V HPS FPGA2SDRAM Clock Queries
Dear Intel and all, Having some very puzzling behavior on HPS SDRAM and FPGA fabric bridge. If a fast clock i.e. 148MHz is running on 128bit AXI3 aka f2h_sdram0 mostly read action. And another AXI3 is using the remain 128bit bus with 144MHz aka f2h_sdram1 mostly on write. As such the system will stuck on distro aka Linux. With all these background could engineer or internal stuffs help. What is the restriction or constraints to use these bus under safe and stable speed? Forgot to provide stable situation: If the write dominated bus is reduced to 100MHz then the system is stable and no stall is found. So this makes a very strong feeling that the write cache is having issue? maybe CMA insufficient? Brian
Main Features Released in 25.1.1
Main Features Released in 25.1.1: Initial support of the Agilex 3 device. Released GSRD for the Agilex 3 C-Series Development Kit. Reference: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-3/c-series/gsrd/ug-gsrd-agx3/ DDR ECC support in the Agilex 5. Support of production Agilex 7 F-Series Crypto device. GSRD for DK-DEV-AGF0123FA dev kit (using production AGFD023R24C2E1VC ) replaces the DK-DEV-AGF027F1ES dev kit (using engineering sample AGFB027R24C2E2VR2). Reference: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-7/f-series/fpga/gsrd/ug-gsrd-agx7f-fpga/ Support of USB 3.1 in Agilex 5 GSRDs. Support of booting from eMMC in ATF to Linux Direct boot for Agilex 5 device. Reference: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/#boot-from-emmc_1 Removed generation of NAND binaries in Agilex 5 GSRD. Will be re-enabled when production devices get released.
Baremetal Example SDMMC makefile failed
Hello, CycloneVsoc with BM environment, SOCEDS 20.1 and ARMDS 2021 I downloaded your bare-metal SDMMC sample, but the build failed when using ARMDS make. Here is the error message: make all arm-altera-eabi-gcc -g -O0 -Wall -Werror -std=c99 -mcpu=cortex-a9 -mfloat-abi=softfp -mfpu=neon -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -Dsoc_cv_av -c sdmmc_demo.c -o sdmmc_demo.o process_begin: CreateProcess(NULL, arm-altera-eabi-gcc -g -O0 -Wall -Werror -std=c99 -mcpu=cortex-a9 -mfloat-abi=softfp -mfpu=neon -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -Dsoc_cv_av -c sdmmc_demo.c -o sdmmc_demo.o, ...) failed. make (e=2) Before making I've point the SOCEDS_DEST_ROOT to my SOC path. And I've opened the embedded_command_shell. Thank you Alex
Inquiry about Transferring DS-5 Node-Locked License
Hello, I would like to transfer the DS-5 node-locked license from my old laptop to a new one. However, I have lost the account credentials (username and password) from the original purchase. Currently, I can only provide the host IDs and the license.lic file. I would like to inquire if it is possible to transfer the license to the new laptop under these circumstances. If transferring is not possible, could you provide information on the cost of repurchasing the license? Additionally, we are currently using the DS-5 Altera Edition. Thank you. Best regards, Judy
Download Intel® SoC FPGA EDS Standard Edition for Windows
The Windows download for the Intel® SoC FPGA EDS Standard Edition seems to be missing from https://fpgasoftware.intel.com/soceds/. The Linux version is available but I cannot find the Windows download. The download buttons at https://www.intel.com/content/www/us/en/software/programmable/soc-eds/overview.html#tab-blade-1-1 also all seem to be broken. Where can I find this download? Thanks.
