hps debug
37 TopicsRelease 26.1.1
Version: Release 26.1.1 PRO Quartus Build/TAG: B130/QPDS26.1.1_REL_GSRD_PR Release Date: August 17, 2026 Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7, Startix® 10 Release Type: Major release/Binary release Binary Release Path: http://releases.rocketboards.org/2026.08/ Release Page: https://github.com/altera-fpga/gsrd-socfpga/releases/tag/QPDS26.1.1_REL_GSRD_PR Major Features Released Agilex™ 5 XEN Hypervisor 5 System Example Design https://altera-fpga.github.io/rel-26.1.1/virtualization/hypervisors/xen/ug-xen-agx5e-premium-065b/ , https://altera-fpga.github.io/rel-26.1.1/virtualization/hypervisors/xen/ug-xen-agx5e-premium-065a/ Agilex™ 5 RYO OPTE System Example Design Agilex™ 5 Quartus Reference Design using VDS Agilex™ 3 Time-Sensitive Networking (TSN): PHY configuration 2 (RGMII from FPGA HVIO) System Example Design Agilex™ 5 Performance Optimized Baseline SED support Agilex™ 5 DataMover / Bridge and Memory Benchmark System Example Design https://altera-fpga.github.io/rel-26.1.1/embedded-designs/agilex-5/e-series/premium-065a/data-mover/ug-data-mover-agx5e-premium-065a/ Agilex™ 3 support of FreeRTOS Agilex™ 5 Terasic DE25-Nano Board System Example Design103Views2likes0CommentsAgilex 5 Premium Dev Kit Ethernet Performance
Hello! We built the golden sample image following the HPS GSRD User Guide with additional packages to profile/evaluate the board and experience performance problems when sending data over ethernet. The test setup is a host connected to the dev kit and sending data to test the throughput. First, we used iperf3 with zero copy flag, which caps at about 940 Mbit/s with almost no variation. Without zero copy, iperf3 caps at about ~880 Mbit/s with some variation down to 629 Mbit/s, see attachment 1.png. With our custom application that also does some additional work, we’d expect about 430-440 Mbit/s, but cap at about 300 Mbit/s, with lots of time spent in kernel again, see attachment 2.png. From the first investigation, we suspect the driver can’t keep up with the generated data and can’t send it fast enough to the host. We are wondering whether we can adjust something in the kernel (driver) or in the image so that we can improve the throughput with heavy workloads. Kind regards!207Views2likes1CommentAgilex 5 premium board - es version - boots with gibberish prompts
Hello dear community, I am trying to boot linux on the Altera Agilex 5 premium board - es version with the pre-built binaries. I followed the documentation still getting prompts in gibberish. Following is a detailed description of the procedure I used. My questions: 1. What am I doing wrong? 2. What should be my debugging flow steps? Detailed description of the procedure to demonstrate the issue: --------------------------------------------------------------------- In order to verify the Agilex 5 SoC premium baord is booting correctly, I used the pre-build binaries per the following instructions of this link: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd- agx5e-premium/#configure-serial-console I followed the paragraphs starting with the title " Exercising Prebuilt Binaries" This page instructs the user to download the pre-built binaries from this release: https://releases.rocketboards.org/2025.08/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/ I followed the instructions of "Booting from SD card". The workstation is Windows 10 machine and the Terminal application is putty. Eventually, when booting the linux per these instruction, I see the first stage boot loader (u-boot spl) is prompting correct font, however the next booting stages are prompting gibberish. Attached is a screenshot (202604262215screenshot.jpg).Solved203Views1like5Comments