2.5G Ethernet Reference Porting inquiries.

Hi, guys~

My customer wants to use the 2.5G Ethernet feature, but unfortunately, they purchased the Agilex5 Premium Kit instead of the Modular Kit. I am currently following the R&D guide with them, but the 88E2110 is not being recognized properly. Which parts should we check?

First, I followed below link. And have built the Reference Design boot images.

https://altera-fpga.github.io/rel-26.1/embedded-designs/agilex-5/e-series/modular-065b/tsn/sgmii_xcvr_3x2.5G/ug-tsn-sgmii-xcvr-3x2.5G-agilex5/

Second, I regenerated the hardware image after updating the Modular design pinout to match the Premium Kit specs. In the Premium schematic, the 88E2110 PHY reset pin is connected to the FPGA, but there was no control logic applied. So, I added logic to release the reset after 20 ms.

Third, in the device tree, I enabled emac0 and disabled emac1 and emac2.

Since the soft MDIO logic remains unchanged, the addresses shouldn't have changed. However, while the emac0 logs appear, the PHY is still not being recognized. Please refer to the attached boot log. Why did they use soft MDIO instead of the native EMAC0 MDIO? Is this a characteristic of 2.5G Ethernet?