New Contributor
New ContributorJust realized you are converting the u-boot-spl file as well, please try using u-boot-spl-dtb.hex, as suggested in the command
New Contributorok，the 7th and 9th steps in the "Operation Steps" remain unchanged. For the 8th step, replace the HPS File with u-boot-spl-dtb.hex.
The generation process was successful. What's the reason for this? It's truly astonishing. It seems that there is no information suggesting that u-boot-spl-dtb.hex is required.
New ContributorYes, my guess is that your conversion as you said in "6. Convert u-boot-spl to u-boot-spl.hex and copy it to the output_files directory" is not aligned, hence the error.
Now, the current information and the recommended flow is the one described in the links I shared with you https://altera-fpga.github.io/rel-25.3/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/#build-core-rbf and https://altera-fpga.github.io/rel-25.3/embedded-designs/stratix-10/sx/soc/fabric-config/ug-linux-fabric-config-s10sx-soc/#build-example
Anyways, I have raised a issue internally so this is better handled by Quartus Programmer instead of a crash.
~E.V.
New ContributorThank you for your response. There are still some doubts. I hope you can offer some suggestions.
Q1：The steps 1 to 5 above remain unchanged(HPS Boot First Mode). At this point, I have obtained the SOF file and the FSBL file. This is the prerequisite condition.
Scene A: If the JTAG loads the SOF file, the HPS cannot start because there is no FSBL information in the SOF file；
Scene B: If it is necessary to be written to flash, HPS can be activated. The SOF files and FSBL files need to be generated as Raw Binary File for HPS Core Configuration (.RBF) and Programmer Object File for Peripheral Configuration (.POF) through the Programming File Generator/Command Line. Finally, the POF file is burned.
Q2：The steps 1 to 5 mentioned above only change the startup sequence; the rest are the same as in Q1.(FPGA Configuration First Mode)
Scene A: If the JTAG loads the SOF file, the HPS cannot start because there is no FSBL information in the SOF file；
Scene B: If it is necessary to be written to flash, HPS can be activated. The SOF file and FSBL file need to be generated as Programmer Object File (.POF) through the Programming File Generator/command line. Finally, the POF file is burned.
I'm not sure if my understanding is correct. It seems that the Quartus Prime Pro 25.1.1 version can only burn POF files, but not JIC files.
New ContributorSo, again as documented in the links.
- "HPS First" mode, you got a "name.core.rbf" and a "name.hsp.jic". The <name>.core.rbf goes into your boot source (this effectively programs the FPGA). The QSPI is programmed the "name.hps.jic", changing the configuration to "JTAGMode" (This is all described in the links I sent)
.............
- "FPGA First" mode you can do two things.
The other option is to write the QSPI Flash with a JIC that has everything
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You don't need the POF
Hopefully this works
