New Contributor
New ContributorWhile I'm investigating if this is a bug in Quartus. Could you try using:
>> quartus_pfg -c <NAME>.sof <NAME>.jic -o device=<DEVICE_NAME> -o flash_loader=<LOADER_NAME> -o hps_path=u-boot-spl-dtb.hex -o mode=ASX4 -o hps=1
Please double ceck your procedures are inline with
https://altera-fpga.github.io/rel-25.3/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/#build-core-rbf and https://altera-fpga.github.io/rel-25.3/embedded-designs/stratix-10/sx/soc/fabric-config/ug-linux-fabric-config-s10sx-soc/#build-example
~E.V.
New ContributorThank you for your reply.
I noticed that the "Build Hardware Design" section in the link would generate two sof files, namely *.sof and *_hps_debug.sof. However, on my end, I don't have the *_hps_debug.sof file.
Could it be that there is something wrong with my project settings?
Here, I can only attempt to convert the file to the jic format using the only_HPS_Baseline.sof file.
The result reported an error. The .sof file is missing the HPS bootloader information.
New ContributorHi!
This is failing because you are missing " -o hps_path=u-boot-spl-dtb.hex"
~E.V.
