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LWH2F Throughput
Dear all, I'm facing the issue that the throughput on the Agilex 5 LWH2F interface appears to be lower compared to Cyclone 5. - I have two custom boards, one is based on Cyclone 5, the other on Agilex 5. - I use a linux OS. The code runs in a linux kernel driver. The code for the driver is the same for both devices. - The memory is mapped using ioremap(), i.e. it is mapped as device memory. - I measure performance by taking a timestamp with ktime_get_ns(), then read/write 10000 uint32 values, then take another timestamp. - I've measured the follwing values - Cyclone5 board read: 47.2 MB/s (million bytes per second or 11.8 million words à 4 byte per second) - Cyclone5 board write: 73.1 MB/s - Agilex5 board read: 24.8 MB/s - Agilex5 board write: 18.8 MB/s - I've noticed that performance varies, depending on the CPU that the process is running on (when measuring in userspace I can explicitly set the cpu affinity; For the kernel driver I've noticed that it is sometimes slower than above, presumably because it's running on a different cpu). - There is a slight difference in the QSYS design: - The Cyclone5 based board: - drives the AXI bus with a 64 MHz clock. - uses the Avalon MM Slave Translator. - The Agilex5 based board: - drives the AXI bus with a 200 MHz clock. - uses the Avalon Memory Mapped Pipeline Bridge Intel FPGA IP. - Our FPGA takes one 64/200 MHz cycle to process the read (readdatavalid). For a write our FPGA doesn't generate a writeresponsevalid, this is handled by the IP block. - I'm using Quartus 25.1.1 for the Agilex 5 design. I'm aware that the LWH2F interface is not intended for high throughput. Also, since the memory is mapped as "Device Memory", every load/store is processed separately and we're not taking advantage of AXI bursts, etc. I'm aware that we could improve performance by using the H2F interface and mapping the memory as normal memory. That said, we have a prooven design and are reluctant to change it unless absolutely neccessary. So I have the following questions: - Is a higher latency expected on Agilex5? (E.g. due to a different architecture of the interconnect) - Have you measured the performance of the LWH2F interface? Can you give me a number on how many transactions per second we can expect? Kind Regards, Eric Opitz
Stratix 10 HPS 8GB SODIMM shared memory for HPS and FPGA
We have custom board with stratix 10 FPGA. the HPS boots from 8GB eMMC and teh linux runs of 2GB soldered DDR4. We also have a 8GB DDR4 SODIMM which we plan to use as a shared memory between the HPS and FPGA. We need help in interfacing this memory with the HPS and FPGA. There are about 8 FPGA modules that need to access the SODIMM along with teh HPS. So total of 8 ports to the memory controller. Can you suggest a solution for this. Is there any muti port wrapper ip for the EMI IP which we can use for this. Also, can the HPS h2f bridge access 8GB memory?
Stratix 10 Linux SD card booting
Hi Altera Community, I tried multiple attempts to boot the SD card from Rocketboard.org. https://releases.rocketboards.org/ I downloaded and booted the SD card with the .wic image file. It only has the .itb file by default in the boot partition. Whenever I try to boot, it asks for the U-Boot.img file. And also it says "failed to load "socfpga_stratix10_socdk.dtb" even if the file is there. And then I compiled my simple HPS design and can easily program the FPGA from the Quartus Programmer (rbf and sof file), but whenever I try to overlay it, like say: echo overlay.dtb > /sys/kernel?config?device-tree/overlays/0/path It says "FPGA manager error, timeout," and so on. Does any community member have notes or steps that you made to boot the SD card of the Stratix 10 FPGA? I am following this link: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderStratix10
Unable to receive OUT packet on USB in device mode
Hello, I am trying to use USB on Cyclone V soc with tinyUSB. I am able to receive SETUP transaction and send device descriptor, but then I cannot receive and acknowledge the next OUT transaction. I see that DOEPINT0.nakintrpt goes to 1, confirming that the device responds NAK to the OUT transaction, but I don't understand why. Here are the settings that are relevant to me : GAHBCFG.dmaen = 0 DCTL.sgoutnak = 1 GRXFSIZ.rxfdep = 0x50 DOEPMSK.xfercomplmsk = 1 GINTMSK.rxflvlmsk = 1 Written before waiting for OUT packet: DOEPCTL0.epena = 1 DOEPCTL0.cnak = 1 DOEPTSIZ0.xfersize = 0 DOEPTSIZ0.pktcnt = 1 I am lacking ideas of where to search or what could cause this behaviour. Is there anything to take care ? Best regards, RomainF2SDRAM fails to synthesize with custom logic
Hello guys, We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-level ports. Does anyone know why this is happening? Also, is there an example design for F2SDRAM available? The GHRD is not very helpful since it only includes the JTAG master. I suspect it might be a design issue, so I even removed the adapter and connected it only within Qsys, but it’s still acting up like this. Does anyone know why this is happening even though everything is clearly declared and connected? Hudson
TSE -> SGDMA -> SOC(through f2sdram)
Hi, I'm trying to transfer an old design with multiple TSEs / SGMDAs and a NIOS to a newer Agilex 5. We are also evaluating the use of the SOC instead of the NIOS in the design. I've made a minimized platform design for it but it fails during synthesis with the notorious error for the f2sdram bus: There is both a 'memory -> streaming' and 'streaming -> memory' sgdma in the design present, so both read and write port on the axi bus should be present. If I connect the SGDMA's to the fpga2hps bus the same error is generated. Are there settings in the SGDMAs that needs to be set to a certain value so that the correct read/write avalon MM/AXI interface is generated?Agilex 5/3 FreeRTOS Heterogeneous SMP SDK Release
Stable Version: v26.1 Quartus Version: 26.1 Supported devices: Agilex™ 3 and Agilex™ 5 Source: https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v26.1-HSMP Release Date: June 24, 2026 Hello Everyone, A new version of the FreeRTOS SDK for Agilex 5/3 is now available. Apart from other fixes and features, the FreeRTOS port now supports heterogeneous SMP for Agilex™ 5 devices. Visit the GitHub repository for instructions on how to get started. Features and Comments Feature Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP Supported Features Limitations / Known Issues A55 boot Yes Yes Yes Yes Single-core boot, Dual-core SMP, Quad-core SMP (Agilex 5) A76 boot NA Yes NA Yes Single-core boot, Dual-core SMP, Quad-core SMP QSPI boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes NAND boot No No No No Clock Manager Yes Yes Yes Yes API to get clock speed of different blocks Reset Manager Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User-defined and free-running modes UART driver Yes Yes Yes Yes Full-duplex TX and RX DMA not supported (planned for future release) I2C driver Yes Yes Yes Yes Master/Slave mode, standard and fast modes QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase I3C driver Yes Yes Yes Yes Master mode, I3C and legacy I2C devices IBI not supported (planned for future release) SPI driver Yes Yes Yes Yes Master/Slave mode write and read NAND driver No No No No SDM Mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes Standard and HS speeds, SDMMC and eMMC devices, FATFS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP, DHCP, IPv4 and IPv6 USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT driver Yes Yes Yes Yes Interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver Yes Yes Yes Yes Enable/Disable bridges Reboot Manager Yes Yes Yes Yes Warm/Cold reboot FPGA Manager Yes Yes Yes Yes FPGA configuration Legend: Yes: Feature available and tested No: Feature not available in SDK NA: Not applicable NT: Not tested Note: If you find any issues, please raise an issue on the GitHub repository. For more support and assistance, visit our website.
