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Fatal error in Module tennm_noc_fabric_adaptor in file .../sim_lib/tennm_agilex7_io96_ncrypt.sv
Hello, I am trying run simulation for our design after instantiated hps subsystem. Code elaborates but i am getting this error, and it comes from encrypted code: # ** Fatal: (vsim-160) /proj/vendors/altera/intelFPGA_pro/24.1/quartus/../devices/sim_lib/tennm_agilex7_io96_ncrypt.sv(132): Null foreign function pointer encountered when calling 'simsf_constra3#_mti_copy_opt_#' Same hps instance simulates properly in tb generated by quartus platform designer. I am not able fine what i am missing in our TB setup. Any help appreciated. Thanks,
S10 hps fpga2sdram bridge low speed
Hello, i have some problems I have a project with stratix 10 with hps I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width Via u-boot smc configured and enabled them, but measured speed is not enough. When I use onle one bridge my speed is approximately 32 gbit/s (bridge and master frequency 350 MHz) But when I use all 3 bridges it becomes 20 gbit/s I use avmm bridge to connect to axi fpga2sdram bridge with 128 bits width, max pending writes 16, max burst size 128, use only write to bridge ECC in emif (hmc) is disabled I tried to use QoS for bridges, set them to bypass P.S. If i use the same board with firmware without hps, i get 130 gbit/s (with disabled hps) Quartus Pro 21.4 Any help would be useful!Agilex 5E - PCIE PERST# pin - failing compilation
Hello! I'm using Critical Link MytiSom Dev Kit. It has the same FPGA as the Altera Dev Kit - A5ED065BB32AE6SR0. I'm adapting the PCIe Root Port example from Altera - I have assigned the PCIe Gen3x4 lanes to bank 4B. I have checked the pin assignments several times but I keep getting failed compilation with the error attached bellow. Any suggestions on what can cause the issue. I have also attached the pin assignments. Thank youAgilex 5 Premium Dev Kit Ethernet Performance
Hello! We built the golden sample image following the HPS GSRD User Guide with additional packages to profile/evaluate the board and experience performance problems when sending data over ethernet. The test setup is a host connected to the dev kit and sending data to test the throughput. First, we used iperf3 with zero copy flag, which caps at about 940 Mbit/s with almost no variation. Without zero copy, iperf3 caps at about ~880 Mbit/s with some variation down to 629 Mbit/s, see attachment 1.png. With our custom application that also does some additional work, we’d expect about 430-440 Mbit/s, but cap at about 300 Mbit/s, with lots of time spent in kernel again, see attachment 2.png. From the first investigation, we suspect the driver can’t keep up with the generated data and can’t send it fast enough to the host. We are wondering whether we can adjust something in the kernel (driver) or in the image so that we can improve the throughput with heavy workloads. Kind regards!Timings eMMC
Hi, latest datasheet of SoC « 813918/2026.01.05 » lists in paragraph « HPS SD/eMMC Timing Characteristics » the constraints of eMMC, applicable to memory component but does not define any timing data in input/output of SoC. There is no Tco min/max of CMD/DATA at SoC output, as well as Tsetup/hold of CMD/DATA at SoC input. Can you provide Tco and Tsetup/hold for eMMC usage (Legacy, HS_SDR, HS_DDR, HS200, HS400) ? thanks
Agilex 5 premium board - es version - boots with gibberish prompts
Hello dear community, I am trying to boot linux on the Altera Agilex 5 premium board - es version with the pre-built binaries. I followed the documentation still getting prompts in gibberish. Following is a detailed description of the procedure I used. My questions: 1. What am I doing wrong? 2. What should be my debugging flow steps? Detailed description of the procedure to demonstrate the issue: --------------------------------------------------------------------- In order to verify the Agilex 5 SoC premium baord is booting correctly, I used the pre-build binaries per the following instructions of this link: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd- agx5e-premium/#configure-serial-console I followed the paragraphs starting with the title " Exercising Prebuilt Binaries" This page instructs the user to download the pre-built binaries from this release: https://releases.rocketboards.org/2025.08/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/ I followed the instructions of "Booting from SD card". The workstation is Windows 10 machine and the Terminal application is putty. Eventually, when booting the linux per these instruction, I see the first stage boot loader (u-boot spl) is prompting correct font, however the next booting stages are prompting gibberish. Attached is a screenshot (202604262215screenshot.jpg).Release 26.1 PRO
Version: Release 26.1 PRO Quartus Build/TAG: B110/QPDS26.1_REL_GSRD_PR Release Date: April 13, 2026 Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7, Startix® 10, Arria® 10 Release Type: Major release/Binary release Binary Release Path: http://releases.rocketboards.org/2026.04/ Release Page: https://github.com/altera-fpga/gsrd-socfpga/releases/tag/QPDS26.1_REL_GSRD_PR Major Features Released Support of SD/eMMC High Speed Modes (SDR104/HS200/HS400) for the in Agilex™ 5 and Agilex™ 3. FreeRTOS release for Agilex™ 5 and Agilex™ 3. Released by 3rd party partner. Support of CPU Benchmarks applications as part of the Agilex™ 5 baseline system example design. Support Mainline + Latest LTS Yocto versions Provide a System Reference Design that boots from eMMC for Agilex™ 7 F-Series Transceiver production Dev kit (agf014e_si_devkit) and for Stratix® 10 H-Tile DevKit (DK-SOC-1SSX-H-D). Provide a Baseline System Reference Design for Agilex™ 5 Premium (SD Card, QSPI, Debug, eMMC and NAND) and Modular (SD Card, QSPI) Production development kits.
Preloader/U-Boot Compilation Failure
General Background: I'm working with a custom board that has an Altera/Intel Cyclone V, SoC FPGA (5CSEBA6U23, similar to the DE10-Nano development kit). The board is already equipped with all the necessary files for a successful boot sequence from a uSD card (FPGA and the ARM processor (HPS)). The Objective: I want to reconfigure the HPS functionality (Mux) for pins 53 and 54 from their current GPIO to CAN BUS. I need to ensure a successful boot from the uSD card with the updated hardware definition and Device Tree. Issue Description: Preloader/U-Boot Compilation Failure After successfully implementing the changes in Quartus and Platform Designer and after successfully generating the BSP files (bsp-editor), I'm attempting to run the "make" command to build the Preloader/U-Boot image. The process starts and creates the uboot-socfpga directory, but the compilation consistently fails with several errors, and the final boot image is not updated. Extension of the successfully completed steps: I've modified the Platform Designer (Qsys) mux functionality to reconfigure the HPS peripheral pins (GPIO53-GPIO54) for CAN BUS functionality. I've integrated the new HPS component into the top-level VHDL project. I've Generate a full VHDL compilation in Quartus. Using the "SoC EDS Command Shell", I launched the BSP-Editor and loaded the updated "settings.bsp" file. After generation, the "hps_isw_handoff" and "generated" directories were updated. I have manually verified the output files (pinmux_config.h) to confirms that CAN1 is now correctly configured in the pin multiplexing settings. What should I do?HPS f2sdram read/write errors
I'm using the Agilex 5 devlopment board and trying to write to the HPS SDRAM with custom logic. I'm already able to write to the other SDRAM (DDR4) on the board with my custom logic going through the AXI4 bus on the hps_subsys, I exported the f2sdram (AXI4 Subordinate) and connected to my custom logic. I can perform read and write cycles and everything flows correctly. I get appropriate response from the f2sdram. however, on both read and write cycles, the f2sdram responds with the RRESP/BRESP of b11, decode error. i have tried to read/write to addresses of 0x0000000000, 0x8800000000, and 0xffff000000 and still get the same response error code. Anything common that I might have missed in my setup?