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SoC FPGA software development (Baremetal, Uboot, ATF, Linux, Zephyr, FreeRTOS, HPS boot and debugging)

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25.3 PRO Release
Version: Release 25.3 PRO Quartus Build/TAG: B109/QPDS25.3_REL_GSRD_PR Release Date: October 10, 2025 Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7, Startix® 10, Arria® 10 Release Type: Major ...
RolandoS_Altera
2 months ago
general
Hps Arch
Hps Boot
Sw Development
192Views
2likes
8Comments

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Cyclone V HPS FPGA2SDRAM Clock Queries
Dear Intel and all, Having some very puzzling behavior on HPS SDRAM and FPGA fabric bridge. If a fast clock i.e. 148MHz is running on 128bit AXI3 aka f2h_sdram0 mostly read action. And another AXI3 is using the remain 128bit bus with 144MHz aka f2h_sdram1 mostly on write. As such the system will stuck on distro aka Linux. With all these background could engineer or internal stuffs help. What is the restriction or constraints to use these bus under safe and stable speed? Forgot to provide stable situation: If the write dominated bus is reduced to 100MHz then the system is stable and no stall is found. So this makes a very strong feeling that the write cache is having issue? maybe CMA insufficient? Brian
BrianSune_Froum
10 hours ago
Arm Processor
embedded peripheral
Hps Debug
operating system
108Views
0likes
9Comments
MSGDMA ST-to-MM: Linux Driver Necessity & F2SDRAM Path Feasibility
Hello everyone, I am currently working on an MSGDMA implementation. I have verified that I can read the MSGDMA CSR and Descriptor registers via the LWH2F bridge using devmem2. My setup is configured in Streaming-to-Memory-Mapped (ST-to-MM) mode. I have two specific questions regarding this setup: 1、Is configuring the MSGDMA Linux kernel driver a mandatory condition for the hardware to function correctly? Is it possible to bypass the driver and configure the MSGDMA to start data transfer directly using devmem2 (user-space access)? 2、I noticed that some implementations write to the PS-side memory via the FPGA-to-HPS bridge. However, my design utilizes the F2SDRAM link, as indicated by the numbered sequence in the attached diagram. Could you please confirm if this architectural approach is feasible?
wangduoyu
1 day ago
Arm Processor
embedded peripheral
general
operating system
56Views
0likes
2Comments
Linux not booting - can't get kernel image
Hi, I'm having trouble booting to Linux after migrating a project to the newest GSRD 2.0 (Quartus 25.3). I'm using an Agilex 5 FPGA E-Series 065B Premium Devkit. The project was based in the GSRD for Quartus 25.1 (QPDS25.1_REL_GSRD_PR) and had a few modifications, working in version 25.1 with the default device-tree. I'm guessing this might be something related to differences in the device-tree between GRSD 2.0 and the previous version ? I've tried looking around but there's so many .dts and .dtsi files that I'm a bit lost. Any advice appreciated.
pmarques
4 days ago
Hps Boot
95Views
0likes
3Comments
Agilex 5 with HPS Cryptographic services and bootflow
Hi I have a question regarding boot flow on agilex 5 with HPS with security in mind. I am aware how this is typically implemented on other SoCs like NXP but as for the Agilex - I just started working on this SoC From what I understand (based on the docs and tf-a source code in particular VAB part) the flow is the following: SDM verfies fsbl signature and loads it SDM releses HPS from reset Fsbl loads next stages (BL31 BL33) each time communicating with SDM through mailbox asking SDM to verify the image signaturure Then we can be sure that we only use legitimate binaries. Am I right? I have found in the agilex 5 product table that some variants are equipped with Cryptographic services and some not. Are these Cryptographic services needed to perform the above flow? If the variant I have is not equipped with such IP is there any other way to securely boot all boot chain up to Linux?
rdrr
5 days ago
Arm Processor
embedded peripheral
Hps Arch
Hps Boot
222Views
0likes
22Comments
Linux mSGDMA Driver Agilex 5
I am trying to use stream-to-memory DMA to move data. This is the design, showing the important Quartus connections: Which corresponds to this address config: # address map write_sdram = 0x00000000 read = NULL (has no meaning in streaming to MM mode) msgdma_csr = 0x22000040 msgdma_descriptor = 0x22000060 # msgdma offsets msgdma_csr_control = 0x4 + 0x22000040 = 0x22000044 msgdma_descriptor_write_low = 0x4 + 0x22000060 = 0x22000064 msgdma_descriptor_length = 0x8 + 0x22000060 = 0x22000068 msgdma_descriptor_control = 0xc + 0x22000060 = 0x2200006c The oscillator IP generates a group of known numbers, so the readbacks change each time - but are predictable and so the hardware is verifiable. In U-Boot; I have verified that this design. This script asks the DMA to make two transfers, and reads back the results each time. SOCFPGA_AGILEX5 # mw 0x22000044 0x1 # Stop Dispatcher SOCFPGA_AGILEX5 # mw 0x22000044 0x20 # Stop descriptors SOCFPGA_AGILEX5 # mw 0x22000044 0x2 # Reset Dispatcher SOCFPGA_AGILEX5 # mw 0x22000064 0x00000000 # Write address SOCFPGA_AGILEX5 # mw 0x22000068 0x8 # Write length in bytes SOCFPGA_AGILEX5 # md 0x22000040 1 # Check status 22000040: 00000002 .... SOCFPGA_AGILEX5 # mw 0x2200006c 0x02000000 # Wait for response SOCFPGA_AGILEX5 # sleep 1 SOCFPGA_AGILEX5 # mw 0x2200006c 0x82000000 # execute SOCFPGA_AGILEX5 # md 0x22000040 1 # Check status 22000040: 00000002 .... SOCFPGA_AGILEX5 # md 0x00000000 1 # read 00000000: 00000000 .... SOCFPGA_AGILEX5 # mw 0x22000044 0x2 # reset SOCFPGA_AGILEX5 # mw 0x2200006c 0x82000000 # execute SOCFPGA_AGILEX5 # md 0x00000000 1 # read 00000000: 67676767 .... When trying to do the same in linux using 'devmem2', I found that the readbacks did not change, so I decided to look for some examples. I found this stream-to-mapped mSGDMA driver built for the Cyclone V, and so re-purposed it. The driver example above both reads and writes to the device using the ‘dd’ utility in linux, but I am for now only interested in the read command. To do so I needed some information... Based on the .qsys design file output of my project, the mSGDMA block generates this interrupt: ... <altera:connection altera:kind="interrupt" altera:version="24.3" altera:start="subsys_hps.f2h_irq0_in" altera:end="msgdma_0.csr_irq"> <altera:connection_parameter altera:parameter_name="irqNumber" altera:parameter_value="2"> </altera:connection_parameter> </altera:connection> ... And according to the interrupt docs, the above csr interrupt value=2 maps to the GIC interrupt 51, which is 19 when referenced from the linux device tree. With this information, I have defined the following mSGDMA element in the .dts: ... msgdma_test: msgdma_test@22000000 { compatible = "msgdma_test"; reg = <0x0 0x22000000 0x0 0x100>; interrupt-parent = <&intc>; interrupts = <0 19 4>; }; ... Which only differs from the original in that it has a different interrupt number, and different base address - also accounting for the lwhps2fpga offset, due to it being the Agilex5 and not the Cyclone. The driver code from the REDS blog post has also been edited in the following way: I need to change a deprecated function in the main driver code: devm_ioremap_nocache to demv_ioremap. I want to see the data which has been moved - to do so have added an info print to the msgdma_read method: printk(KERN_INFO "MSGDMA: Read buffer content: %.*s\n", (int)read_ret, (char*)data->dma_buf_rd); There is only 1 interrupt, so we set data->msgdma1_irq = platform_get_irq(pdev, 0); Since there is no ability coded to fabric to perform msgdma_write - we can also remove memory allocations, remaps and references to msgdma0 and other write related objects. I think the following shows that the DMA is firing interrupts, and so I am confident that I have connected the correct interrupt: cat /proc/interrupts | grep msgdma 50: 2 0 0 0 GICv3 51 Level msgdma1 However, when looking at the kernel outputs after requesting reads via dd: $ dd if=/dev/msgdma_test of=/dev/null bs=8 count=1 $ dmesg | tail [ ... ] MSGDMA: Read buffer (hex): 00 00 00 00 00 00 00 00 [ ... ] MSGDMA: Read buffer (hex): 00 00 00 00 00 00 00 00 The driver code in question is included in msgdma.c and header_msgdma.c, attached to the post (This forum does not seem to like .h files...) I was hoping someone might have an idea of where I went wrong! Any helpers are much appreciated! Thanks for your time, K
Solved
K606
7 days ago
Sw Development
Sw Library
2.2KViews
0likes
9Comments
Operating system kernel-level FPGA bridge communication
We are using a custom (Agilex 5) platform and need to access the FPGA bridges from the Linux kernel. We are unable to locate the corresponding device tree nodes or modifications required to access these memory-mapped regions. We're aware of the devmem2 package, but we want to access the FPGA from the kernel side without relying on it. Please guide us on how to configure the device tree and use kernel-level commands or interfaces to access the HPS-to-FPGA and Lightweight HPS-to-FPGA bridges. configuration from Linux. CONFIG_OF_RESOLVE y CONFIG_OF_OVERLAY y CONFIG_OF_CONFIGFS y CONFIG_FPGA_MGR_STRATIX10_SOC y CONFIG_FPGA_BRIDGE y CONFIG_FPGA_REGION y CONFIG_OF_FPGA_REGION y CONFIG_OVERLAY_FS y
Arun_Prabakatr
13 days ago
embedded peripheral
operating system
197Views
0likes
11Comments
Sending serial commands on DB9 Arria 10 SoC FPGA
I am attempting to send serial based commands using the RS-232 protocol on the DB9 connector on the Arria 10 but do not know which device to use within my C program. I've opened "/dev/tty0" and can send appropriate commands "AT+CGMM\r" but these commands are sent out the J10 UART1 (HPS) on the board and not the DB9. I'm unable to read "/dev/ttyS1" within my c program. I've tried various other devices without luck. I've also set status to "okay" on serial0@ffc02000. In file: ./arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts and rebuild the dtb and placed on SD card. I've looked in Non-8250 serial port support in .config but haven't modified the kernel. Previously, I did enable the FTDI in the kernel for another device and got that working correctly. Any suggestions will be greatly appreciated. Thank you. stty -F /dev/ttyS1 stty: /dev/ttyS1: Input/output error
sfillingim
17 days ago
Hps Debug
Sw Development
68Views
0likes
3Comments
Arria 10 SoC Dev Kit Baremetal HPS examples issue & workflow
Hi, I recently acquired an Arria 10 SoC dev kit but I'm really struggling to run either the examples on embedded-software/bare-metal or the ones included in SoC EDS pro 20.1, trying to follow the instructions for both of them, they seem to rely on a old version of SoC EDS which included within ARM DS-5 and the toolchain, but now SoC EDS & ARM DS are separated and I cannot build the examples. With the new applications the flow for using this examples should remain the same? I mean: use Pogrammer to program the included .sof inside ghrd (or generate a updated one) -> open ARM-DS from SoC-EDS with environmental variables assigned and build with new toolchain arm-none-eabi -> run from ARM-DS (can i without license?) Seems like most of the tools used for running this examples have been discontinued (for example ) so at this point I don't know which workflow should I actually follow. PD: finally I was able to generate de application.axf from this example Altera-SoCFPGA-HardwareLib-16550-CV-GNU with an old toolchain but I don't know how to program it without a license, for now I don't want to debug anything, just do some simple tests printing by uart
keloke98
17 days ago
Arm Processor
general
Hps Boot
Sw Development
179Views
0likes
15Comments
Agilex 5 EMAC GMII loopthrough: signals are not toggling in Fabric
I am trying to route GMII signals through the Agilex5 HPS to the Fabric. In the .dts I am using, I have the following settings for the two EMACs: &gmac0 { status = "okay"; mac-mode = "gmii"; phy-mode = "gmii"; // must be added, and if no PHY, then add fixed link //phy-handle = <&emac0_phy0>; max-frame-size = <9000>; fixed-link { speed = <1000>; full-duplex; }; mdio0 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; emac0_phy0: ethernet-phy@0 { reg = <0>; }; }; }; &gmac1 { status = "okay"; mac-mode = "gmii"; phy-mode = "gmii"; //phy-handle = <&emac1_phy0>; max-frame-size = <9000>; fixed-link { speed = <1000>; full-duplex; }; mdio0 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; emac1_phy0: ethernet-phy@0 { reg = <0>; }; }; }; In the RTL I am connecting the two EMACs as followed: logic user_clk_pll_125, user_clk_pll_25, user_clk_pll_2_5; // 1G / 100M / 10M (* noprune *) logic [7:0] tx_dummy_counter; (* noprune *) logic emac0_mac_tx_clk_o_wire, emac0_mac_tx_clk_i_wire, emac0_mac_rx_clk_wire, emac0_mac_rst_tx_n_wire, emac0_mac_rst_rx_n_wire; (* noprune *) logic emac0_mac_txen_wire, emac0_mac_txer_wire, emac0_mac_rxdv_wire, emac0_mac_rxer_wire, emac0_mac_col_wire, emac0_mac_crs_wire; (* noprune *) logic [7:0] emac0_mac_rxd_wire; (* noprune *) logic [2:0] emac0_mac_speed_wire; (* noprune *) logic [7:0] emac0_mac_txd_o_wire; (* noprune *) logic [7:0] rx_dummy_counter; (* noprune *) logic emac1_mac_tx_clk_o_wire, emac1_mac_tx_clk_i_wire, emac1_mac_rx_clk_wire, emac1_mac_rst_tx_n_wire, emac1_mac_rst_rx_n_wire; (* noprune *) logic emac1_mac_txen_wire, emac1_mac_txer_wire, emac1_mac_rxdv_wire, emac1_mac_rxer_wire, emac1_mac_col_wire, emac1_mac_crs_wire; (* noprune *) logic [7:0] emac1_mac_rxd_wire; (* noprune *) logic [2:0] emac1_mac_speed_wire; (* noprune *) logic [7:0] emac1_mac_txd_o_wire; assign emac0_mac_rx_clk_wire = emac1_mac_tx_clk_o_wire; // 1G assign emac1_mac_rxdv_wire = emac0_mac_txen_wire; assign emac1_mac_rxer_wire = emac0_mac_txer_wire; assign emac1_mac_rxd_wire = emac0_mac_txd_o_wire; assign emac1_mac_col_wire = 1'b0; assign emac1_mac_crs_wire = 1'b0; assign emac0_mac_rx_clk_wire = emac0_mac_tx_clk_o_wire; // 1G assign emac0_mac_rxdv_wire = emac1_mac_txen_wire; assign emac0_mac_rxer_wire = emac1_mac_txer_wire; assign emac0_mac_rxd_wire = emac1_mac_txd_o_wire; assign emac0_mac_col_wire = 1'b0; assign emac0_mac_crs_wire = 1'b0; The GMII signals are exported from the Agilex HPS as followed: When the system boots, the following can be seen is dmesg: [ 1.443647] socfpga-dwmac 10810000.ethernet: Adding to iommu group 0 [ 1.450679] socfpga-dwmac 10810000.ethernet: IRQ eth_wake_irq not found [ 1.457291] socfpga-dwmac 10810000.ethernet: IRQ eth_lpi not found [ 1.463542] socfpga-dwmac 10810000.ethernet: RX VLAN HW Stripping [ 1.469741] socfpga-dwmac 10810000.ethernet: SMTG Hub Cross Timestamp supported [ 1.477398] socfpga-dwmac 10810000.ethernet: User ID: 0x76, Synopsys ID: 0x31 [ 1.484534] socfpga-dwmac 10810000.ethernet: XGMAC2 [ 1.489489] socfpga-dwmac 10810000.ethernet: DMA HW capability register supported [ 1.496943] socfpga-dwmac 10810000.ethernet: RX Checksum Offload Engine supported [ 1.504396] socfpga-dwmac 10810000.ethernet: COE Type 1 [ 1.509603] socfpga-dwmac 10810000.ethernet: TX Checksum insertion supported [ 1.516623] socfpga-dwmac 10810000.ethernet: TSO supported [ 1.522089] socfpga-dwmac 10810000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 1.530076] socfpga-dwmac 10810000.ethernet: device MAC address 42:ca:f5:1e:55:80 [ 1.537533] socfpga-dwmac 10810000.ethernet: Enabled L3L4 Flow TC (entries=16) [ 1.544737] socfpga-dwmac 10810000.ethernet: Enabled RFS Flow TC (entries=10) [ 1.551847] socfpga-dwmac 10810000.ethernet: TSO feature enabled [ 1.557831] socfpga-dwmac 10810000.ethernet: SPH feature enabled [ 1.563815] socfpga-dwmac 10810000.ethernet: TX COE limited to 2 tx queues [ 1.570665] socfpga-dwmac 10810000.ethernet: Using 40/40 bits DMA host/device width [ 1.581335] socfpga-dwmac 10820000.ethernet: Adding to iommu group 1 [ 1.588338] socfpga-dwmac 10820000.ethernet: IRQ eth_wake_irq not found [ 1.594945] socfpga-dwmac 10820000.ethernet: IRQ eth_lpi not found [ 1.601179] socfpga-dwmac 10820000.ethernet: RX VLAN HW Stripping [ 1.607380] socfpga-dwmac 10820000.ethernet: SMTG Hub Cross Timestamp supported [ 1.614905] socfpga-dwmac 10820000.ethernet: User ID: 0x76, Synopsys ID: 0x31 [ 1.622027] socfpga-dwmac 10820000.ethernet: XGMAC2 [ 1.626982] socfpga-dwmac 10820000.ethernet: DMA HW capability register supported [ 1.634436] socfpga-dwmac 10820000.ethernet: RX Checksum Offload Engine supported [ 1.641890] socfpga-dwmac 10820000.ethernet: COE Type 1 [ 1.647097] socfpga-dwmac 10820000.ethernet: TX Checksum insertion supported [ 1.654117] socfpga-dwmac 10820000.ethernet: TSO supported [ 1.659583] socfpga-dwmac 10820000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 1.667568] socfpga-dwmac 10820000.ethernet: device MAC address 3e:47:0a:4f:7b:96 [ 1.675024] socfpga-dwmac 10820000.ethernet: Enabled L3L4 Flow TC (entries=16) [ 1.682221] socfpga-dwmac 10820000.ethernet: Enabled RFS Flow TC (entries=10) [ 1.689330] socfpga-dwmac 10820000.ethernet: TSO feature enabled [ 1.695314] socfpga-dwmac 10820000.ethernet: SPH feature enabled [ 1.701298] socfpga-dwmac 10820000.ethernet: TX COE limited to 2 tx queues [ 1.708147] socfpga-dwmac 10820000.ethernet: Using 40/40 bits DMA host/device width [ 1.718293] socfpga-dwmac 10830000.ethernet: Adding to iommu group 2 [ 1.725245] socfpga-dwmac 10830000.ethernet: IRQ eth_wake_irq not found [ 1.731850] socfpga-dwmac 10830000.ethernet: IRQ eth_lpi not found [ 1.738075] socfpga-dwmac 10830000.ethernet: RX VLAN HW Stripping [ 1.744242] socfpga-dwmac 10830000.ethernet: SMTG Hub Cross Timestamp supported [ 1.751730] socfpga-dwmac 10830000.ethernet: User ID: 0x76, Synopsys ID: 0x31 [ 1.758854] socfpga-dwmac 10830000.ethernet: XGMAC2 [ 1.763807] socfpga-dwmac 10830000.ethernet: DMA HW capability register supported [ 1.771261] socfpga-dwmac 10830000.ethernet: RX Checksum Offload Engine supported [ 1.778712] socfpga-dwmac 10830000.ethernet: COE Type 1 [ 1.783917] socfpga-dwmac 10830000.ethernet: TX Checksum insertion supported [ 1.790936] socfpga-dwmac 10830000.ethernet: TSO supported [ 1.796400] socfpga-dwmac 10830000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 1.804372] socfpga-dwmac 10830000.ethernet: Enabled L3L4 Flow TC (entries=16) [ 1.811565] socfpga-dwmac 10830000.ethernet: Enabled RFS Flow TC (entries=10) [ 1.818673] socfpga-dwmac 10830000.ethernet: TSO feature enabled [ 1.824656] socfpga-dwmac 10830000.ethernet: SPH feature enabled [ 1.830639] socfpga-dwmac 10830000.ethernet: TX COE limited to 2 tx queues [ 1.837487] socfpga-dwmac 10830000.ethernet: Using 40/40 bits DMA host/device width ... [ 11.730428] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 11.747001] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-1 [ 11.770275] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-2 [ 11.778338] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-3 [ 11.782322] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-4 [ 11.787412] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-5 [ 11.790998] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-6 [ 11.796018] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-7 [ 11.813781] fpga_manager fpga0: Stratix10 SOC FPGA Manager registered [ 11.913063] socfpga-dwmac 10830000.ethernet eth2: PHY [stmmac-2:01] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL) [ 11.913393] socfpga-dwmac 10830000.ethernet eth2: No Safety Features support found [ 11.913478] socfpga-dwmac 10830000.ethernet eth2: IEEE 1588-2008 Advanced Timestamp supported [ 12.001908] socfpga-dwmac 10830000.ethernet eth2: registered PTP clock [ 12.007839] socfpga-dwmac 10830000.ethernet eth2: FPE workqueue start [ 12.007940] socfpga-dwmac 10830000.ethernet eth2: configuring for phy/rgmii-id link mode [ 12.155854] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 12.159161] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-1 [ 12.180998] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-2 [ 12.191086] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-3 [ 12.199787] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-4 [ 12.208205] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-5 [ 12.218464] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-6 [ 12.229854] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-7 [ 12.247722] socfpga-dwmac 10820000.ethernet eth1: No Safety Features support found [ 12.247967] socfpga-dwmac 10820000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported [ 12.331440] socfpga-dwmac 10820000.ethernet eth1: registered PTP clock [ 12.332900] socfpga-dwmac 10820000.ethernet eth1: FPE workqueue start [ 12.332987] socfpga-dwmac 10820000.ethernet eth1: configuring for fixed/gmii link mode [ 12.343803] socfpga-dwmac 10820000.ethernet eth1: Link is Up - 100Mbps/Full - flow control off [ 12.344209] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready [ 12.449807] of-fpga-region soc:base_fpga_region: FPGA Region probed [ 12.469882] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 12.479649] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-1 [ 12.482568] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-2 [ 12.490255] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-3 [ 12.493314] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-4 [ 12.501735] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-5 [ 12.514200] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-6 [ 12.536765] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-7 [ 12.582718] socfpga-dwmac 10810000.ethernet eth0: No Safety Features support found [ 12.583005] socfpga-dwmac 10810000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported [ 12.591157] socfpga-dwmac 10810000.ethernet eth0: registered PTP clock [ 12.601012] socfpga-dwmac 10810000.ethernet eth0: FPE workqueue start [ 12.601201] socfpga-dwmac 10810000.ethernet eth0: configuring for fixed/gmii link mode [ 12.611650] socfpga-dwmac 10810000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off [ 12.615095] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready ... (this log was from testing 100M, but the same occurs for 1G) In signal tap, no wires are toggled (even though it seems the output clocks are fine) Please help!
K606
26 days ago
embedded peripheral
general
Hps Debug
232Views
0likes
10Comments
Agilex 5 HPS porting guide
Hi, I'm wondering - what are the components that need to be adapted for a custom board based on Agilex 5. For the background e.g. on NXP Layerscape LS1028a in order to bring up a custom board we had to provide board-specific code in TF-A (DDR bring up for our memory config) and u-boot. I'm wondering what does it look like on Agilex5-based boards? I'm not talking about obvious things like device-tree but rather other parts like board-specific TF-A code and so on. Would be grateful to for some information that would allow me to estimate the necessary work. Also I'm talking about FPGA-first scenario if that matters.
Solved
rdrr
29 days ago
Arm Processor
Hps Arch
Hps Boot
78Views
0likes
2Comments