Regarding the Footprint creation of AGFB022R24C2E2V
Hi For the AGFB022R24C2E2V The package drawing specifies a solder resist opening of Ø0.50 ± 0.02 mm, but it does not specify the recommended PCB pad diameter. Could you please provide the recommended PCB land pattern, including the copper pad diameter and whether the pads should be solder mask defined (SMD) or non-solder mask defined (NSMD)? Addition please provide the Allegro footprint for AGFB022R24C2E2V
A3C* BSDL updates available?
Hello, There are several of the A3CZ, A3CU and A3CV* families which are fail compilation with syntax errors on pins duplicated (usually K24 and K25). and then a most have errors in their use of port_grouping. Are there updates available? Regars, Tom iBSDL - Intellitech BSDL Compiler Version 14.25 Copyright (C) 1993-2026 Intellitech Corp. All rights reserved. ERROR: Device package pin mappings: Duplicate pin id K24 ( IEEE Std 1149.1 Rule B.8.7.3 a). ERROR: Device package pin mappings: Duplicate pin id K25 ( IEEE Std 1149.1 Rule B.8.7.3 a). INFO: Associated Port REFCLK_GTSL1A_RX_n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH3n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH2n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH0n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH1n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden ERROR: Associated port GTSL1A_TX_CH3n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH3n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) ERROR: Associated port GTSL1A_TX_CH2n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH2n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) ERROR: Associated port GTSL1A_TX_CH1n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH1n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) ERROR: Associated port GTSL1A_TX_CH0n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH0n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) The compile failed.
URGENT SUPPORT FOR FMD DATA COLLECTION
Hi Team, I am Siddesh Chavan from the NetApp Component Engineering Team. As part of our component compliance review and documentation update process, we are reviewing the Lotes Co. Ltd part. We kindly request your support in providing the information requested for the components listed in the attached file. Please acknowledge receipt of this email and confirm whether you can provide the requested details. Your support will help us keep our records accurate and up to date. Thank you for your support and cooperation. We look forward to your response. Regards, Siddesh ChavanErrors in Agilex A3 A3CZ025BB18A BSDL
Hello, I'm using Intellitech free BSDL compiler, and it gives an error because the PIN_BEHAVIOR for 1149.6 pins are not described. This makes it unclear what pins have IEEE 1149.6 capability and its a syntax error. These are version 1.0 from 2025. It may be good to check them before distribution. Regards, Tom. attribute AIO_Pin_Behavior of Agilex_A3CZ025BB18A: entity is -- ***************************************************************************************** -- * DESIGN WARNING * -- ***************************************************************************************** attribute DESIGN_WARNING of Agilex_A3CZ025BB18A: entity is iBSDL - Intellitech BSDL Compiler Version 14.25 Copyright (C) 1993-2026 Intellitech Corp. All rights reserved. Line:1667 ERROR: Line:1668 attribute DESIGN_WARNING of Agilex_A3CZ025BB18A: entity is ^ Line:1669 "This Agilex_A3CZ025BB18ABSDL file supports 1149.1 and 1149.6"& Missing QUOTE '"' or CONCATENATE '&' character in a QUOTED_STRING. This type of error can be hard for the compiler to point to the correct line number. ERROR: Check that all the ATTRIBUTES are in the correct order. BSDL has a strict order and a common error is that the attributes are not in the correct order See B.8.11 ERROR: Illegal structure to the BSDL. See B.8.1.1 Syntax The order is fixed per B.8.1.1 as follows: <BSDL description>::= entity <component name> is <generic parameter> (see B.8.2) <logical port description> (see B.8.3) <standard use statement> (see B.8.4) {<use statement>} (see B.8.5) <component conformance statement> (see B.8.6) <device package pin mappings> (see B.8.7) [<grouped port identification>] (see B.8.8) <scan port identification> (see B.8.9) [<compliance enable description>] (see B.8.10) <instruction register description> (see B.8.11) [<optional register description>] (see B.8.12) [<register access description>] (see B.8.13) <boundary-scan register description> (see B.8.14) [<runbist description>] (see B.8.15) [<intest description>] (see B.8.16) {<BSDL extensions>} (see B.8.17) [<design warning>] (see B.8.18) end <component name>;
Agilex 7 (F-tile/R-tile) PCIe Gen5 RX Compliance Test Issue -some lanes can't enter Loopback
Hi Teams, We are currently working on a custom PCIe Add-in Card based on Agilex 7 (F-tile / R-tile). Note that the FPGA firmware is provided to us by our end customer. Design Context: According to our customer, the provided FPGA firmware utilizes a PCIe Endpoint ROM, which includes a built-in function to handle the transition into loopback mode. The customer believes this loopback mechanism should function properly. Current Status: PCIe Gen5 TX Compliance Test: Passed successfully. PCIe Gen5 RX Compliance Test: Encountered issues during our recent testing at an external lab. Problem Description: During the Rx test, we observed that lanes 0, 1, 7, and 15 successfully entered loopback mode and passed. However, the remaining lanes (Lanes 2-6 and 8-14) could not be initiated or triggered into loopback mode by the BERT. According to the lab's experience, this type of issue usually requires a specific or test-oriented FPGA firmware version (such as a special configuration for LTSSM or compliance mode) to properly conduct the PCIe Rx compliance test across all lanes. Our Questions: Does the built-in PCIe Endpoint ROM loopback function in Agilex 7 F-tile/R-tile require physical Lane 0 to be active in order to trigger loopback on other lanes? Since the test lab uses a 1-lane or 2-lane BERT and moves the lanes sequentially (meaning Lane 0 will be in Electrical Idle when testing Lane 2/3), will this cause the EP ROM's state machine to hang or ignore the BERT's TS1/TS2 loopback commands? Are there any known limitations, workarounds, or specific IP parameters we need to modify to allow individual lane loopback entry without relying on Lane 0? Any insights or suggestions would be greatly appreciated, as we need to sync this back to our customer's firmware team. Thanks!
EP4CGX22CF19C8N Failure Short D8 to C8
We encounter failure for EP4CGX22CF19C8N related to pin D8 to C8. Failure observed during turn on stage on system level. Further verification leading to EP4CGX22CF19C8N shorted related from pin D8 to C8. We conducted ABA swap and the issue resolve. Failure follows the bad part. Table below indicates measurement comparison between good unit and failed unit. Please advise what would be the caused for this issue? Condition Reading (from U57.D8 to U58.C8) Good Part OL (Open Loop) Bad Part 2.1 Ohm
Request for ESD and Reflow Information
Hello, To optimize the manufacturing of our electronic boards, we are looking for ESD and reflow information for the following devices: A5ED043BB32AI4S A5ED028BB32AI4S We have a valid CNDA in place and would like to know whether any ESD characterization data is available for these components. Could someone please provide the ESD ratings according to JEDEC standards: HBM (JESD22-A114 / JS-001) CDM (JESD22-C101 / JS-002) We are also interested in the reflow soldering constraints, including: Maximum peak reflow temperature Time at peak temperature Maximum number of reflow cycles If detailed characterization data is not available, could you please point us to the maximum allowed overshoot and input transition time specifications for this product family, either from the datasheet or any available application documentation? Thank you for your support.
