Reset Release IP VHDL code not working

Hi,
the message tells about VHDL syntax errors, a bit different from "not working".

It's generally a good idea to fix syntax errors from top to bottom, succeeding erors may be just aftereffects.

First errors are incorrect component declarations.
Component declarations follows this scheme

component_declaration ::=
component identifier [ is ]
[ local_generic_clause ]
[ local_port_clause ]
end component [ component_simple_name ] ;

There's no place for signals in component declaration.

You'll later notice that your component declaration, besides unexpected signal declaration are also incomplete because they don't
declare all ports of the respective components.

We would e.g. expect

component rr_ip
port(
ninit_done : out std_logic
);
end component;

Just to give you a starting point. You should have a VHDL text book or tutorial at hand.

Hello,

Seems to me that the Reset Release IP is correctly instantiated.

Based on the error message, the problem is due to the sys_pll component instantiation on line 26.

You were trying to connect to ports that do not exist in the sys_pll component.

Please check if the connections are correct. These threads may be helpful for you: https://www.edaboard.com/threads/problem-with-using-components-in-vhdl.374664/

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Error-10349-VHDL-Association-List-error-at-mult16bit-vhd-41/m-p/94175

Regards,

Nurina

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

Hi,

Now your Reset Release IP VHDL file does not look like Reset Release IP at all.

Are the reset release IP and sys_pll the same? Why are you combining them?

The error message is saying that you need to have an entity for both RRIP and sys_pll.

You may find these useful:

https://fpgatutorial.com/vhdl-entity-architecture-library/

https://vhdlwhiz.com/entity-instantiation-and-component-instantiation/

https://nandland.com/entity-and-architecture/

Regards,

Nurina

O.k., resetRelease.vhd (second screenshot) contains entity declaration, but many syntax errors. Obviously it has been never compiled.

Not intended to be exhaustive:
- each entity declaration needs its own library statement

- all signals used in the arcitecture must be declared, either as port or internal signal
- process needs begin statement
- signal assignment uses <= rather than => operator

- can't write port signals with direction "in"

It seems to me that you filled architecture bodies with arbitrary signal assignments instead of implementing meaningful code function. I'd rather try to write entities that serve a useful purpose.

Regarding your other question, you don't necessarily need compoenent decalarations when instantiating VHDL entities, you can use
this syntax
u1: entity work.sys_pll instead of u1: sys_pll

Alos explained in the links given by Nurina

You don't show what errors you're getting now, but here are the many issues I see:

Where is the code for component clockdiv?

Why does sys_pll.vhd have a signal in its port list named my_reset? I presume you added this in for some reason. Assuming this is generated from an IP, you should not be editing the top-level code for the IP. In the IP Parameter Editor, you should go to Generate -> Show Instantiation template and use the template there to instantiate the IP exactly as it's generated. There is no reason to edit the top-level code for a generated IP. For a basic PLL, there are only 4 signals: refclk and rst inputs, and locked and outclk_0 outputs. What are sys_clk and rst_in since there is already outclk_0 and rst? And why is locked bidirectional? It's an output status signal from the PLL. And there is no bidirectional logic in the core of an FPGA. The component declaration should simply be (from the instantiation template):

COMPONENT sys_pll is

PORT (refclk, rst: IN STD_LOGIC;

locked, outclk_0: OUT STD_LOGIC);

END COMPONENT;

ninit_done is an output of the reset release IP and yet you are connecting it to an input port in the toplevel, an input pin of the device, which makes no sense. It should be connected to reset inputs of the instantiated components or used as a status indicator. And what is sys_rst supposed to be doing? You declare it and then it's not used anywhere. The reset release IP should be used as just a status indicator that device initialization is complete. You can use it as a reset signal, but it won't ever go low again during normal operation of the device so it can't be used as a warm reset.

If you're not using the locked signal of the PLL, just leave it out of the port map. You're basically connecting a signal to itself when you say locked => locked, which makes no sense.

Speaking of port mapping, you have it backwards for the PLL. The first signal name is the name of the component's port. The signal after "=>" is the signal in this level of the design that the lower-level port is connecting to. So your PLL instantiation should probably look like this:

u1: sys_pll PORT MAP (rst_in => my_reset, clk => clk, outclk_0 => iclk);

Even this isn't perfect because what is the point of clockdiv? You can divide a clock using the PLL itself instead of needing oclk and iclk.

I highly suggest you check out some VHDL training: https://cdrdv2.intel.com/v1/dl/getContent/652842

Hi Drew,

Since this involves a few vhd files, can you share the .qar file of your project?

To generate this, go to Project>Archive project.

This is so that I can add the necessary code changes and you can review them.

Regards,

Nurina

Hi Drew,

Is the sys_pll suppose to be just a PLL? Where did you get this code?

Based on line 15, you are latching the sys_rst with locked and rst but there is a syntax error due to locked being an output port of the sys_pll. I'm not sure what you wanted the sys_pll to describe.

I have resolved the errors and used an IOPLL IP in place of the sys_pll.vhd. You can make changes to the IOPLL settings as you wish. I'm attaching the .qar file here shortly.

Regards,

Nurina

Hi,

I checked and it's because toplevel.vhd is not set as top level entity.

Set the toplevel.vhd as top level entity and it will resolve the RES-10204 - Reset Release Instance Count Check warning.

Ultimately you should check the RTL viewer/simulation to see if this is the circuit/functionality you were going for.

Regards,

Nurina

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

Hi Drew,

I think you can ignore the Evaluation Mode warning. It doesn't seem like you're using it anyway. More info about it here: https://www.intel.com/content/www/us/en/docs/programmable/683502/17-1/an-320-using.html

You got those warnings because the reset release IP isn't connected to those registers, and in fact it isn't connected to anything in your project at all. I wasn't sure how you want to connect the reset release IP and I'm not an expert on this IP's usage. I was just helping out to fix the syntax errors.

What do you want to use this IP for? How do you want to connect it to the other modules?

You may find this useful: https://www.intel.com/content/dam/support/us/en/programmable/support-resources/bulk-container/pdfs/literature/an/archives/an891-19-3.pdf

Regards,

Nurina